TMS320F280049: The best practice to clear TZFLG caused by DCAEVT1 and DCBEVT1 on F280049

Sheldon He

Part Number: TMS320F280049

Hi expert,

On F280049, my customer use CMPSS6 as a source for EPWM7's DCAEVT1 and DCBEVT1. Further more DCAEVT1 and DCBEVT1 will One-shot trip EPWM7 with both channel in high state. They clear trip zone flag (TZFLG) in a 40KHz control loop. In the control loop, they check bit DCAEVT1 and DCBEVT1 of TZCLR register for EPWM7 module and clear flag like this:

const bool level2_ov_tz = (EPwm7Regs.TZCLR.all & DCAEVT1_MASK) ? true : false;
………
………
………
if(level2_ov_tz)
    {
EALLOW;
      EPwm1Regs.TZCLR.all = EPwm1Regs.TZFLG.all;
      EPwm2Regs.TZCLR.all = EPwm2Regs.TZFLG.all;
      EPwm3Regs.TZCLR.all = EPwm3Regs.TZFLG.all;
      EPwm4Regs.TZCLR.all = EPwm4Regs.TZFLG.all;
      EPwm5Regs.TZCLR.all = EPwm5Regs.TZFLG.all;
      EPwm6Regs.TZCLR.all = EPwm6Regs.TZFLG.all;
      EPwm7Regs.TZCLR.all = EPwm7Regs.TZFLG.all;              
      EDIS;
}
…………
…………
…………

But, they find sometime EPWM was get trip with a register reading of TZFLG = 4 which is unexpected. After they changed to clear the TZCLR in bit, the problem never occurs again. Could you help me find the possible cause? May be it is something related the signal delay?

Thanks

Sheldon

over 6 years ago

0 Nima Eskandari over 6 years ago

TI__Guru 52020 points

Quick follow up questions.

What do you mean TZFLG=4 is unexpected? That is just showing the ONE-SHOT trip has occurred.
What do you mean by "changed to clear the TZCLR in bit"?

Thank you,

Nima Eskandari

0 Sheldon He over 6 years ago in reply to Nima Eskandari

TI__Expert 8585 points

Hi Nima,

To clarify, TZFLG=4 should be cleared in the control loop with the code shown above, but for some reason, it will be not cleared as expected. This is the problem.
As for the second question. At first, they clear TZFLG using method like "EPwm1Regs.TZCLR.all = EPwm1Regs.TZFLG.all;", which they found sometimes the clear operation is unsuccessful. So they clear TZFLG in another method like "EPwm1Regs.TZCLR.bit.DCBEVT1 = EPwm1Regs.TZFLG.bit.DCBEVT1;" then they never get a problem again. So I need to know the reason behind.

Thanks
Sheldon

0 Sheldon He over 6 years ago in reply to Nima Eskandari

TI__Expert 8585 points

Nima,

The code I provided before should have
"const bool level2_ov_tz = (EPwm7Regs.TZFLG.all & DCAEVT1_MASK) ? true : false;"
instead of
"const bool level2_ov_tz = (EPwm7Regs.TZCLR.all & DCAEVT1_MASK) ? true : false;"

Thanks

0 Sheldon He over 6 years ago in reply to Nima Eskandari

TI__Expert 8585 points

Hi Nima.
In brief, could you help me understanding the relationship between "EPwm1Regs.TZFLG.bit.OST" and "EPwm1Regs.TZOSTFLG.bit.OST1"? Is there a gap between the setting of these two registers when an one shot event comes?
Thanks

0 Sheldon He over 6 years ago in reply to Sheldon He

TI__Expert 8585 points

Hi Nima,
This is a related thread but the answer is not confirmed yet.
e2e.ti.com/.../693559

0 Nima Eskandari over 6 years ago in reply to Sheldon He

TI__Guru 52020 points

Sheldon,

As far as the FLAG, we dont document any difference in which one gets set first when it comes to TZFLG and TZOSTFLG. But I have always cleared TZOSTFLG first then the TZFLG. That is because you check TZFLG to see if there is an interrupt, then use TZOSTFLG to see which oneshot caused the interrupt if it was OST that caused it, clear the specific OST that caused it. Then clear the TZFLG for OST to complete the steps.

As far as the .all and the .bit difference, I have asked the team and I currently dont have an answer for you that is certain so we have to do more digging. Here is what we need to do.

Log all the flags before clearing.

Log all the flags after clearing.

See if they got cleared.

Log all the flags again.

And lets see what we have.

Plus, lets look at the disassembly for using the bit vs using the .all and see the difference is.

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TMS320F280049: The best practice to clear TZFLG caused by DCAEVT1 and DCBEVT1 on F280049