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TMS320F28379D: F28379D EPWM's submodule DC Module: Register TZCLR can't clear the DCAEVT1&DCBEVT1 bit in TZFLG Register

Part Number: TMS320F28379D

I am combine tne CMPSS module  with EPWM's DC module to implement the  hardware protection,the code is show below (please ignore the Chinese,^_^):

//---------------------------------------------------------------------------------------------------------------------------------------------

EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0x0011; //3,TRIP4
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x0011; //3,TRIP4
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2; //010:DCAH = high,DCAL = don't care, DC A Event 1 Selection
EPwm1Regs.TZDCSEL.bit.DCBEVT1 = 2; //010:DCBH = high,DCBL = don't care, DC B Event 1 Selection
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; //1, Source is passed through asynchronously

EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0x0011; //3,TRIP4
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x0011; //3,TRIP4
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 2; //010:DCAH = high,DCAL = don't care, DC A Event 1 Selection
EPwm2Regs.TZDCSEL.bit.DCBEVT1 = 2; //010:DCBH = high,DCBL = don't care, DC B Event 1 Selection
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; //1, Source is passed through asynchronously

EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0x0011; //3,TRIP4
EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x0011; //3,TRIP4
EPwm3Regs.TZDCSEL.bit.DCAEVT1 = 2; //010:DCAH = high,DCAL = don't care, DC A Event 1 Selection
EPwm3Regs.TZDCSEL.bit.DCBEVT1 = 2; //010:DCBH = high,DCBL = don't care, DC B Event 1 Selection
EPwm3Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; //1, Source is passed through asynchronously

#define TZSEL_INIT_STATE1 ENABLE_TZ1_OST+ENABLE_DCAEVT1_OST+ENABLE_DCBEVT1_OST

#define TZCTL_INIT_STATE ( TZA_FORCE_LO + TZB_FORCE_LO )

EPwm1Regs.TZSEL.all = TZSEL_INIT_STATE1;
EPwm2Regs.TZSEL.all = TZSEL_INIT_STATE1;
EPwm3Regs.TZSEL.all = TZSEL_INIT_STATE1;

/* Init Trip Zone Control Register*/
EPwm1Regs.TZCTL.all = TZCTL_INIT_STATE; //TZA_FORCE_LO + TZB_FORCE_LO
EPwm2Regs.TZCTL.all = TZCTL_INIT_STATE; //TZA_FORCE_LO + TZB_FORCE_LO
EPwm3Regs.TZCTL.all = TZCTL_INIT_STATE; //TZA_FORCE_LO + TZB_FORCE_LO

//---------------------------------------------------------------------------------------------------------------------------------------------

The question is that I just can't clear the Flag bit in TZFLG Register with the TZCLR Register, and the logic is confuse.

Why??? Is there any bug in my configuration code?

My brain is gonna blow, please saving me!!