Compiler/TMS320F28379D: TMS320F28379D Delfino simultaneous ADC sampling FFT/DFT SW library

Leo,

My replies to your questions below.

1. Is it correct that all sample points data have to be buffered in memory prior calling RFFT_f32() function?
Yes, this is why the 2837x_RFFT example has RFFTin1Buf of size FFT_SIZE.
However, you will notice that 2837x_RFFT_ADC and 2837x_RFFT_ADC_RT examples have RFFTin1Buf of size 2 x FFT_SIZE. This is because they implement the FFT in Ping-Pong fashion, where the FFT is library is processing the Ping buffer, and the ADC is filling up the Pong buffer, and vice versa.

Note, however, that the assumption is that the device's 12-bit ADC is used. I don't see an issue with using a 16-bit ADC (external) if the right hooks are installed.

2. If Q1 statement is valid, may I know what is the memory size required for our use case (4x ADC, N=8k, align/unaligned FFT)? Is F28379D memory adequate to support this operation without XRAM?

You can do this calculation yourself and refer to the device datasheet to check if the memory requirements are met. Just note that for the aligned case, you will need double the input buffer size.

3. Description of RFFT_f32() in fpu_rfft.h state that this function supports N-pt N = 2^{n}, n = 5 : 10, can it support n = 13 (N = 8k = 2^13)?

Yes it can. The user guide needs to be updated (I have filed a JIRA for this already). The user guide refers to sizes for which Twiddle factor precomputed tables are available. Beyond that, the twiddle factor tables will have to be computed through a function call.

4. What is the difference between RFFT_f32(u) and RFFT_adc_f32(u)?

Please read sections 5.11 and 5.12 of the user guide. In addition to what I mentioned in my reply to question 1 above, you will note in the user guide that the ADC case uses a separate struct to hold the input data.

5. as per my understanding, F28379d is capable of running 4 channels FFT parallel, are there available sources of sample codes to refer to?
These examples in the C2000Ware library are all we have. But the extension from single to multiple channels would be straighforward in software. The constraints are Memory and MIPS. If there's enough Memory and MIPS (at the sample rate at which you want the FFTs computed), you can run the FFTs.

6. Does TI have optimized DFT calc method or implementation code?
Not sure I understand the question. The FFT is the optimized way of calculating the DFT. The FFT library assembly source is available for the customer to see (C:\ti\c2000\C2000Ware_1_00_06_00\libraries\dsp\FPU\c28\source\fft)

7. Is there better approach (performance/memory usage) for our use case? E.g. DFT/FFT calc on the fly while taking ADC readings.
As I mentioned in my reply to question 1, on the fly is essentially what is happening with the Ping-Pong approach. If you are buffering 8k samples at 1Msps, you will have some latency (8ms).

If your questions have been answered, it would help if you could mark my Answer as Verified.

Thanks,
Sira