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Original question:

TMS320F280049: CPU timers performancies

TMS320F280049: DMA to DAC and CPU timer

yann volpelier
Prodigy 180 points
Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE,

Hi and thanks for your analyse on the CPU timers limitations

In fact this first post is to understand one behavior on the example

C:\ti\c2000\C2000Ware_1_00_06_00\device_support\f2807x\examples\cpu1\buffdac_sine_dma\cpu01

which I have adapted to the TMS320F280049 (I will post to explain you the adaptation performed and bugs fixed).

The aim is to obtain a sinus signal of 100kHz (see e2e.ti.com/support/microcontrollers/c2000/f/171/t/763056). First I have tried with PWM but it is limited under around 33kHz if the duty cycle is updated during CPU INT. So after the response of your colleague, I am working on a DMA and DAC solution.


The limitation of the CPU timer over 1 MHz (e2e.ti.com/support/microcontrollers/c2000/f/171/t/765888)

explains the latency of the pulse generated at the start of the DMA transfer (see following capture with sinus signal around 104kHz and 8 MHz sampling frequency and 80 samples per period)

Why should the DMA be triggered by a timer ?
So due to the timer limitation, could the DMA be triggered at 4MHz (or higher) frequency by a ePWM ?

Those questions refer to the code line : "DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = DMA_TINT0;    // Timer0 is DMA trigger"

Regards
Yann
  • 0
    TI__Mastermind 28275 points
    Hi Yann,

    The frequency of the generated sine is not only a factor of the trigger frequency. It's a combination of the sinetable_step_size, length_of_the_sine_table and trigger_frequency. Keep in mind that the triggered DMA is updating the DAC so there is an upper limit on how quickly that should happen. This upper limit is bounded by the DAC settling time of 2us. Theoretically, that gives you a maximum update rate of 500KHz. 1MHz update rate is probably fine for the smaller sine_table steps but i wouldn't go any higher than that.

    The example code has the formula -> outputFreq_hz = (samplingFreq_hz/SINE_TBL_SIZE)*tableStep. Hence, other ways to increase the output frequency is by increasing the step_size, reducing the table_size or a combination of the 2.
  • 0 in reply to Frank Ankapong
    TI__Mastermind 28257 points
    Hi Frank,

    I am the FAE working with Yann. Assuming we are generating a 100 kHz, 3 V pk-pk sine wave, the maximum slew rate of this sine wave is 2 pi f Vpk = 1.9 V/us. Has the F28004x buffered DAC has a minimum specified output slew rate of 2.8 V/us, we should be fine sampling at a frequency higher than 500 kHz or even 1 MHz as you suggested, don't you think so?

    The point in sampling at the highest frequency reasonably possible is to minimize the cost of the external analog filter and still have a signal as clean as possible from harmonics (EMC considerations).

    Please let us know your thoughts.


    Thanks,
    François.
  • 0 in reply to Francois Charlot
    TI__Mastermind 28275 points
    Hi François,

    You shouldn't exceed the DAC's maximum update rate. For the DAC to output a voltage, it's a combination of slew rate and settling time, not just slew rate. Before the DAC settling time elapses, the DAC output voltage is still changing. It will be up to you to decide if just slewing is enough for your project but I recommend you stick to the settling time.
  • 0 in reply to Frank Ankapong
    TI__Mastermind 28257 points

    Hi Frank,

    I am still struggling with this limitation on the settling time, when each step I will output is a fine one that should only be constrained by the slew rate, not by the settling time which is linked to a large step like full scale or 1/4 full scale.

    I have looked at what our DAC experts say about Understanding your DAC's speed limit. Their conclusion was that "In most high-accuracy applications, settling time is the effective update rate for the DAC." Is this something I could apply to my case, where the slope of each step is well below the minimum specified slew rate?


    Thanks,
    François.

  • 0 in reply to Francois Charlot
    TI__Mastermind 28275 points
    Hi François,

    Yes, settling time is the effective maximum update rate for the DAC. If you ran the DAC at a very high update rate, one issue you will see is that the pk-to-pk sine output is much less than expected. This is because the DAC's output is not given enough time to reach it's target before the next target comes in.

    One other thing to note is, if you write a value to the DAC, the output doesn't start changing immediately. It takes a few 100ns to start changing due to the internal state machine. This delay is not accounted for in the slew rate but is accounted for in the settling time.

    One last point, the DAC's AC performance in the datasheet was obtained by outputting a sine that is given enough time to settle between each step. There is a possibility that if the settling time spec is violated, the output sine will have worse AC performance.