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Original question:
Tool/software: TI C/C++ Compiler
Dear All,
I am trying to copy all the compiler sections from FLASH to RAM in TMS320F2812.
I have studied and used the material available at
But I am unable to make my DSP run. After using the files mentioned in the above link, DSP is getting trapped at 0x000066 address and without even entering main(). I tried copying one by one compiler sections into RAM. Only copying of .text section into RAM is creating the problem. Other sections are working fine with the given code. Any leads on this would be very helpful.
Thanks!
Kashyap Gundlapalli
Hi Ozino Odharo,
Thanks for the reply!
Console output has no errors.
The issue got solved yesterday surprisingly by disconnecting and restarting the controller after loading the code.
Once restarted, if I load the same code into the controller, I was able to debug else it is not working. I am not completely sure of the reason behind this behavior but I find it difficult to disconnect, restart, reconnect and re-load the program to debug small small changes during development and debugging phases.
Can you please suggest any better way to do this?
Thanks again!
Kashyap Gundlapalli
Dear Ozino,
Thanks for the reply. I have commented the "Initflash()" function provided by TI that deals with flash settings. Please find the related code part below:
void HardwareInit(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// Disable the watchdog
WatchDog();
// Initialize the PLLCR to 0xA
InitPll(0xA);
// Initialize the peripheral clocks
InitPeripheralClocks();
// Step 2. Initalize GPIO:
InitGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
InitPieVectTable();
// Copy time critical code and Flash setup code to RAM
// This includes the following ISR functions: EvaTimer1(), EvaTimer2()
// EvbTimer3 and and InitFlash();
// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
// symbols are created by the linker. Refer to the F2812.cmd file.
//MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
// Step 4. Initialize all the Device Peripherals:
InitPeripherals(); //
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
//InitFlash();
// Enable PIE group 2 interrupt 4 for T1PINT
PieCtrlRegs.PIEIER2.all = M_INT4;
// Enable PIE group 1 interrupt 6 for ADCINT
PieCtrlRegs.PIEIER1.all = M_INT6;
IER |= M_INT2; // Enable interrupt core line 2 (INT2)
IER |= M_INT1; // Enable ADC interrupt
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
}
.c file is also attached here for your reference
/*****************************************************************************/
/* */
/* INNERVE POWER SOLUTIONS */
/* */
/*****************************************************************************/
/* */
/* Module name: HARDWARE.C */
/* */
/* Programmer: Saikrishna Kashyap */
/* */
/* Date: 2018-04-25 */
/* */
/* Description: Hardware functions. */
/* */
/*****************************************************************************/
#define HARDWARE
#include "hardware.h"
void InitPeripherals(void);
void InitPieVectTable(void);
void InitPll(Uint16 val);
void InitPeripheralClocks(void);
void InitPieCtrl(void);
void InitGpio(void);
void InitEv(void);
void InitAdc(void);
// Watchdog functions
void KickDog(void);
void WatchDog(void);
//void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
void InitFlash(void);
Uint16 CsmUnlock(void);
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // Reserved space
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
// Non-Peripheral Interrupts
INT13_ISR, // XINT13 or CPU-Timer 1
INT14_ISR, // CPU-Timer2
DATALOG_ISR, // Datalogging interrupt
RTOSINT_ISR, // RTOS interrupt
EMUINT_ISR, // Emulation interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
USER12_ISR, // User Defined trap 12
// Group 1 PIE Vectors
PDPINTA_ISR, // EV-A
PDPINTB_ISR, // EV-B
rsvd_ISR,
XINT1_ISR,
XINT2_ISR,
ADCINT_ISR, // ADC
TINT0_ISR, // Timer 0
WAKEINT_ISR, // WD
// Group 2 PIE Vectors
CMP1INT_ISR, // EV-A
CMP2INT_ISR, // EV-A
CMP3INT_ISR, // EV-A
T1PINT_ISR, // EV-A
T1CINT_ISR, // EV-A
T1UFINT_ISR, // EV-A
T1OFINT_ISR, // EV-A
rsvd_ISR,
// Group 3 PIE Vectors
T2PINT_ISR, // EV-A
T2CINT_ISR, // EV-A
T2UFINT_ISR, // EV-A
T2OFINT_ISR, // EV-A
CAPINT1_ISR, // EV-A
CAPINT2_ISR, // EV-A
CAPINT3_ISR, // EV-A
rsvd_ISR,
// Group 4 PIE Vectors
CMP4INT_ISR, // EV-B
CMP5INT_ISR, // EV-B
CMP6INT_ISR, // EV-B
T3PINT_ISR, // EV-B
T3CINT_ISR, // EV-B
T3UFINT_ISR, // EV-B
T3OFINT_ISR, // EV-B
rsvd_ISR,
// Group 5 PIE Vectors
T4PINT_ISR, // EV-B
T4CINT_ISR, // EV-B
T4UFINT_ISR, // EV-B
T4OFINT_ISR, // EV-B
CAPINT4_ISR, // EV-B
CAPINT5_ISR, // EV-B
CAPINT6_ISR, // EV-B
rsvd_ISR,
// Group 6 PIE Vectors
SPIRXINTA_ISR, // SPI-A
SPITXINTA_ISR, // SPI-A
rsvd_ISR,
rsvd_ISR,
MRINTA_ISR, // McBSP-A
MXINTA_ISR, // McBSP-A
rsvd_ISR,
rsvd_ISR,
// Group 7 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 8 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 9 PIE Vectors
SCIRXINTA_ISR, // SCI-A
SCITXINTA_ISR, // SCI-A
SCIRXINTB_ISR, // SCI-B
SCITXINTB_ISR, // SCI-B
ECAN0INTA_ISR, // eCAN
ECAN1INTA_ISR, // eCAN
rsvd_ISR,
rsvd_ISR,
// Group 10 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 11 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 12 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
};
// Functions that will be run from RAM need to be assigned to
// a different section. This section will then be mapped to a load and
// run address using the linker cmd file.
//#pragma CODE_SECTION(InitFlash, "ramfuncs");
//---------------------------------------------------------------------------
// Hardware:
//---------------------------------------------------------------------------
void HardwareInit(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// Disable the watchdog
WatchDog();
// Initialize the PLLCR to 0xA
InitPll(0xA);
// Initialize the peripheral clocks
InitPeripheralClocks();
// Step 2. Initalize GPIO:
InitGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
InitPieVectTable();
// Copy time critical code and Flash setup code to RAM
// This includes the following ISR functions: EvaTimer1(), EvaTimer2()
// EvbTimer3 and and InitFlash();
// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
// symbols are created by the linker. Refer to the F2812.cmd file.
//MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
// Step 4. Initialize all the Device Peripherals:
InitPeripherals(); //
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
//InitFlash();
// Enable PIE group 2 interrupt 4 for T1PINT
PieCtrlRegs.PIEIER2.all = M_INT4;
// Enable PIE group 1 interrupt 6 for ADCINT
PieCtrlRegs.PIEIER1.all = M_INT6;
IER |= M_INT2; // Enable interrupt core line 2 (INT2)
IER |= M_INT1; // Enable ADC interrupt
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
}
void WatchDog(void)
{
EALLOW;
SysCtrlRegs.WDCR = 0x0068;
//SysCtrlRegs.WDKEY = 0x0055;
//SysCtrlRegs.WDKEY = 0x00AA;
EDIS;
}
//---------------------------------------------------------------------------
// PLL:
//---------------------------------------------------------------------------
// This function initializes the PLLCR register.
void InitPll(Uint16 val)
{
volatile Uint16 iVol;
if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
EALLOW;
SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until the PLL is
// stable. Once the PLL is stable the CPU will switch to the new PLL value.
//
// This switch time is 131072 CLKIN cycles as of Rev C silicon.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// If this function is run from waitstated memory, then the loop count can
// be reduced as long as the minimum switch time is still met.
// iVol is volatile so the compiler will not optimize this loop out
//
// The watchdog should be disabled before this loop, or fed within
// the loop.
WatchDog();
// Wait lock cycles.
// Note, This loop is tuned to 0-waitstate RAM memory. If this
// function is run from wait-stated memory such as Flash or XINTF,
// then the number of times through the loop can be reduced
// accordingly.
for(iVol= 0; iVol< ( (131072/2)/12 ); iVol++)
{
}
}
}
//---------------------------------------------------------------------------
// Peripheral Clocks:
//---------------------------------------------------------------------------
// This function initializes the clocks to the peripheral modules.
// First the high and low clock prescalers are set
// Second the clocks are enabled to each peripheral.
// To reduce power, leave clocks to unused peripherals disabled
// Note: If a peripherals clock is not enabled then you cannot
// read or write to the registers for that peripheral
void InitPeripheralClocks(void)
{
EALLOW;
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0003; // 40ns or 25MHz
SysCtrlRegs.LOSPCP.all = 0x0003; // 40ns or 25MHz
// Peripheral clock enables set for the selected peripherals.
SysCtrlRegs.PCLKCR.bit.EVAENCLK = 1;
SysCtrlRegs.PCLKCR.bit.EVBENCLK = 1;
SysCtrlRegs.PCLKCR.bit.SCIAENCLK = 1;
SysCtrlRegs.PCLKCR.bit.SCIBENCLK = 1;
SysCtrlRegs.PCLKCR.bit.MCBSPENCLK = 1;
SysCtrlRegs.PCLKCR.bit.SPIENCLK = 1;
SysCtrlRegs.PCLKCR.bit.ECANENCLK = 1;
SysCtrlRegs.PCLKCR.bit.ADCENCLK = 1;
EDIS;
}
//---------------------------------------------------------------------------
// GPIO:
//---------------------------------------------------------------------------
void InitGpio(void)
{
EALLOW;
// Set up GPIO
GpioMuxRegs.GPAMUX.all = 0x073F;
GpioMuxRegs.GPADIR.all = 0xE0FF;
// GPAMUX.bit. GPADIR.bit. Function I/O | Signal
// PWM1_GPIOA0 = 1; GPIOA0 = 1; // PWM1, output | U+
// PWM2_GPIOA1 = 1; GPIOA1 = 1; // PWM2, output | U-
// PWM3_GPIOA2 = 1; GPIOA2 = 1; // PWM3, output | V+
// PWM4_GPIOA3 = 1; GPIOA3 = 1; // PWM4, output | V-
// PWM5_GPIOA4 = 1; GPIOA4 = 1; // PWM5, output | W+
// PWM6_GPIOA5 = 1; GPIOA5 = 1; // PWM6, output | W-
// T1PWM_GPIOA6 = 0; GPIOA6 = 1; // T1PWM, output | E
// T2PWM_GPIOA7 = 0; GPIOA7 = 1; // IOA7, output | -POWER_EN
// CAP1Q1_GPIOA8 = 1; GPIOA8 = 0; // IOA8, input | ENC 1
// CAP2Q2_GPIOA9 = 1; GPIOA9 = 0; // IOA9, input | ENC 2
// CAP3QI1_GPIOA10 = 1; GPIOA10 = 0; // IOA10, input | ENC 3
// TDIRA_GPIOA11 = 0; GPIOA11 = 0; // IOA11, input | -PF
// TCLKINA_GPIOA12 = 0; GPIOA12 = 0; // IOA12, input |
// C1TRIP_GPIOA13 = 0; GPIOA13 = 1; // IOA13, output | DC_RELAY
// C2TRIP_GPIOA14 = 0; GPIOA14 = 1; // IOA14, output | FAN
// C3TRIP_GPIOA15 = 0; GPIOA15 = 1; // IOA15, output | BCC
GpioMuxRegs.GPAQUAL.all = 0x0000; // No input Qualification
GpioMuxRegs.GPBMUX.all = 0x0000;
GpioMuxRegs.GPBDIR.all = 0x7CD7;
// GPBMUX.bit. GPBDIR.bit. Function I/O | Signal
// PWM7_GPIOB0 = 0; GPIOB0 = 1; // IOB0, output |
// PWM8_GPIOB1 = 0; GPIOB1 = 1; // IOB1, output |
// PWM9_GPIOB2 = 0; GPIOB2 = 1; // IOB2, output |
// PWM10_GPIOB3 = 0; GPIOB3 = 0; // IOB3, input | -DESAT
// PWM11_GPIOB4 = 0; GPIOB4 = 1; // IOB4, output | Test Point
// PWM12_GPIOB5 = 0; GPIOB5 = 0; // IOB5, input |
// T3PWM_GPIOB6 = 0; GPIOB6 = 1; // IOB6, output | Test Point
// T4PWM_GPIOB7 = 0; GPIOB7 = 1; // IOB7, output |
// CAP4Q1_GPIOB8 = 0; GPIOB8 = 0; // IOB8, input | POWER_SWITCH or CAP_0 on card
// CAP5Q2_GPIOB9 = 0; GPIOB9 = 0; // IOB9, input | CAP_1 or -BCC_DESAT
// CAP6QI2_GPIOB10 = 0; GPIOB10 = 1; // IOB10, output |
// TDIRB_GPIOB11 = 0; GPIOB11 = 1; // IOB11, output |
// TCLKINB_GPIOB12 = 0; GPIOB12 = 1; // IOB12, output | HEART BEAT
// C4TRIP_GPIOB13 = 0; GPIOB13 = 1; // IOB13, output |
// C5TRIP_GPIOB14 = 0; GPIOB14 = 1; // IOB14, output |
// C6TRIP_GPIOB15 = 0; GPIOB15 = 0; // IOB15, input |
GpioMuxRegs.GPBQUAL.all = 0x0000; // No input Qualification
GpioMuxRegs.GPDMUX.all = 0x0000;
GpioMuxRegs.GPDDIR.all = 0xFFFF;
// GPDMUX.bit. GPDDIR.bit. Function I/O | Signal
// Not used and hence all are configured as outputs
GpioMuxRegs.GPDQUAL.all = 0x0000; // No input Qualification
GpioMuxRegs.GPEMUX.all = 0x0000;
GpioMuxRegs.GPEDIR.all = 0xFFFF;
// GPEMUX.bit. GPEDIR.bit. Function I/O | Signal
// Not used and hence all are configured as outputs
GpioMuxRegs.GPEQUAL.all = 0x0000; // No input Qualification
GpioMuxRegs.GPFMUX.all = 0x0000;
GpioMuxRegs.GPFDIR.all = 0x43DF;
// GPFMUX.bit. GPFDIR.bit. Function I/O | Signal
// SPISIMOA_GPIOF0 = 0; GPIOF0 = 1; // IOF0, output | GPIOF0 - Test Point
// SPISOMIA_GPIOF1 = 0; GPIOF1 = 1; // IOF1, output | GPIOF1 - Test Point
// SPICLKA_GPIOF2 = 0; GPIOF2 = 1; // IOF2, output | GPIOF2 - Test Point
// SPISTEA_GPIOF3 = 0; GPIOF3 = 1; // IOF3, output | GPIOF3 - Test Point
// SCITXDA_GPIOF4 = 0; GPIOF4 = 1; // IOF4, output | GPIOF4 - Test Point
// SCIRXDA_GPIOF5 = 0; GPIOF5 = 0; // IOF5, input |
// CANTXA_GPIOF6 = 0; GPIOF6 = 1; // IOF6, output |
// CANRXA_GPIOF7 = 0; GPIOF7 = 1; // IOF7, output |
// MCLKXA_GPIOF8 = 0: GPIOF8 = 1; // IOF8, output | GPIOF8 - Test Point
// MCLKRA_GPIOF9 = 0; GPIOF9 = 1; // IOF9, output | GPIOF9 - Test Point
// MFSXA_GPIOF10 = 0; GPIOF10 = 0; // IOF10, input |
// MFSRA_GPIOF11 = 0; GPIOF11 = 0; // IOF11, input |
// MDXA_GPIOF12 = 0; GPIOF12 = 0; // IOF12, input |
// MDRA_GPIOF13 = 0; GPIOF13 = 0; // IOF13, input |
// XF_GPIOF14 = 0; GPIOF14 = 1; // IOF14, output |
GpioMuxRegs.GPGMUX.all = 0x0000;
GpioMuxRegs.GPGDIR.all = 0x0010;
// GPGMUX.bit. GPGDIR.bit. Function I/O | Signal
// SCITXDB_GPIOG4 = 0; GPIOG4 = 1; // IOG4, output |
// SCIRXDB_GPIOG5 = 0; GPIOG5 = 0; // IOG5, input |
EDIS;
}
//---------------------------------------------------------------------------
// PieCtrl:
//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
void InitPieCtrl(void)
{
// Disable Interrupts at the CPU level:
DINT;
// Disable the PIE
PieCtrlRegs.PIECRTL.bit.ENPIE = 0;
// Clear all PIEIER registers:
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
// Clear all PIEIFR registers:
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
}
//---------------------------------------------------------------------------
// Enable Interrupts:
//---------------------------------------------------------------------------
// This function enables the PIE module and CPU interrupts
//
void EnableInterrupts()
{
// Enable the PIE
PieCtrlRegs.PIECRTL.bit.ENPIE = 1;
// Enables PIE to drive a pulse into the CPU
PieCtrlRegs.PIEACK.all = 0xFFFF;
// Enable Interrupts at the CPU level
EINT;
}
//---------------------------------------------------------------------------
// Pie Vector Table:
//---------------------------------------------------------------------------
void InitPieVectTable(void)
{
int16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 128; i++)
*Dest++ = *Source++;
EDIS;
// Enable the PIE Vector Table
PieCtrlRegs.PIECRTL.bit.ENPIE = 1;
}
//---------------------------------------------------------------------------
// Peripherals:
//---------------------------------------------------------------------------
void InitPeripherals(void)
{
InitEv();
InitAdc();
}
//---------------------------------------------------------------------------
// Event Manager:
//---------------------------------------------------------------------------
void InitEv(void)
{
// Setup EVA-T1, timeBase 40ns (HSPCLK)
//-----------------------------------------------------------------------
// Uses PWM outputs with dead-time enabled
// Uses T1CMPR for ENABLE
EvaRegs.T1PR = CARRIER_PERIOD; // Period with up-down counter
EvaRegs.T1CNT = 0x0000; // Clear counter
EvaRegs.T1CMPR = EvaRegs.T1PR; // OFF initially
EvaRegs.CMPR1 = EvaRegs.T1PR; // OFF initially
EvaRegs.CMPR2 = EvaRegs.T1PR; // OFF initially
EvaRegs.CMPR3 = EvaRegs.T1PR; // OFF initially
EvaRegs.GPTCONA.all = 0x0140; // T1/T2 PWM/CMPR enable,
//EvaRegs.GPTCONA.bit.rsvd = 0; // b15 , 0 Reserved
//EvaRegs.GPTCONA.bit.T2STAT = 0; // b14 , 0 GP Timer 2 status (Read only)
//EvaRegs.GPTCONA.bit.T1STAT = 0; // b13 , 0 GP Timer 1 status (Read only)
//EvaRegs.GPTCONA.bit.T2CTRIPE = 0; // b12 , 0->T2CTRIP disabled
//EvaRegs.GPTCONA.bit.T1CTRIPE = 0; // b11 , 0->T1CTRIP disabled
//EvaRegs.GPTCONA.bit.T2TOADC = 0; // b10-b9, 00->No T2 event starts ADC
//EvaRegs.GPTCONA.bit.T1TOADC = 2; // b8-b7 , 10->Setting of Timer1 period interrupt flag starts ADC
//EvaRegs.GPTCONA.bit.TCMPOE = 1; // b6 , 1->Enable T1/T2 PWM/CMPR by compare logic. Bit active only if EXTCON(0)=0, otherwise reserved
//EvaRegs.GPTCONA.bit.T2CMPOE = 0; // b5 , 0 Reserved if EXTCON(0) = 0.
//EvaRegs.GPTCONA.bit.T1CMPOE = 0; // b4 , 0 Reserved if EXTCON(0) = 0.
//EvaRegs.GPTCONA.bit.T2PIN = 0; // b3-b2 , 00->Forced low, pol. of GP Timer 2 compare output (Used as GPIO signal: -POWER_ENABLE)
//EvaRegs.GPTCONA.bit.T1PIN = 0; // b1-b0 , 00->Forced low, pol. of GP Timer 1 compare output
EvaRegs.ACTRA.all = 0x0000; // All PWMs are set to forced low state
//EvaRegs.ACTRA.bit.SVRDIR = 0; // b15 , 0->Space vector PWM rotation (Not used)
//EvaRegs.ACTRA.bit.D = 0; // b14-b12, 0->Space vector bits (Not used)
//EvaRegs.ACTRA.bit.CMP6ACT = 0; // b11-b10,00->PWM6 Forced Low as Inverter is OFF initially
//EvaRegs.ACTRA.bit.CMP5ACT = 0; // b9-b8 ,00->PWM5 Forced Low as Inverter is OFF initially
//EvaRegs.ACTRA.bit.CMP4ACT = 0; // b7-b6 ,00->PWM4 Forced Low as Inverter is OFF initially
//EvaRegs.ACTRA.bit.CMP3ACT = 0; // b5-b4 ,00->PWM3 Forced Low as Inverter is OFF initially
//EvaRegs.ACTRA.bit.CMP2ACT = 0; // b3-b2 ,00->PWM2 Forced Low as Inverter is OFF initially
//EvaRegs.ACTRA.bit.CMP1ACT = 0; // b1-b0 ,00->PWM1 Forced Low as Inverter is OFF initially
EvaRegs.DBTCONA.all = 0x01F4; // Enable, DeadTime Value = 1.28us
//EvaRegs.DBTCONA.bit.rsvd2 = 0; // b15-b12, 0 Reserved
//EvaRegs.DBTCONA.bit.DBT = 1; // b11-b8 ,0000->Dead-band timer period -> 1*32*40ns = 1.28us
//EvaRegs.DBTCONA.bit.EDBT3 = 1; // b7 , 1->Enable for PWM5 & PWM6
//EvaRegs.DBTCONA.bit.EDBT2 = 1; // b6 , 1->Enable for PWM3 & PWM4
//EvaRegs.DBTCONA.bit.EDBT1 = 1; // b5 , 1->Enable for PWM1 & PWM2
//EvaRegs.DBTCONA.bit.DBTPS = 5; // b4-b2 , 101->Dead-band timer prescaler -> 32
//EvaRegs.DBTCONA.bit.rsvd1 = 0; // b1-b0 , 0 Reserved
EvaRegs.COMCONA.all = 0xAA00; // CMPR reload @UF & @P,ACTR reload @UF, No SV, Compare Enable
//EvaRegs.COMCONA.bit.CENABLE = 1; // b15 , 1->Compare enable
//EvaRegs.COMCONA.bit.CLD = 1; // b14-b13,01->Compare reload when T1CNT is 0 (Underflow) and T1PR (Period)
//EvaRegs.COMCONA.bit.SVENABLE = 0; // b12 , 0->Space vector PWM disabled
//EvaRegs.COMCONA.bit.ACTRLD = 2; // b11-b10,01->Load ACTR immediately
//EvaRegs.COMCONA.bit.FCOMPOE = 1; // b9 , 1->Full compare outputs enabled. Bit active only if EXTCON(0) = 0, otherwise reserved
//EvaRegs.COMCONA.bit.PDPINTASTATUS = 0;// b8 , 0 PDPINTA status (Read only)
//EvaRegs.COMCONA.bit.FCMP3OE = 0; // b7 , 0 Reserved if EXTCON(0) = 0.
//EvaRegs.COMCONA.bit.FCMP2OE = 0; // b6 , 0 Reserved if EXTCON(0) = 0.
//EvaRegs.COMCONA.bit.FCMP1OE = 0; // b5 , 0 Reserved if EXTCON(0) = 0.
//EvaRegs.COMCONA.bit.rsvd = 0; // b4-b3 ,00 Reserved
//EvaRegs.COMCONA.bit.C3TRIPE = 0; // b2 , 0->C3TRIP disabled
//EvaRegs.COMCONA.bit.C2TRIPE = 0; // b1 , 0->C2TRIP disabled
//EvaRegs.COMCONA.bit.C1TRIPE = 0; // b0 , 0->C1TRIP disabled
EvaRegs.T1CON.all = 0x0842; // Continuous up/down, enable timer, enable compare, reload @UF & @P
//EvaRegs.T1CON.bit.FREE = 0; // b15 , 0->|
//EvaRegs.T1CON.bit.SOFT = 0; // b14 , 0->|Stop immediately on emulator suspend
//EvaRegs.T1CON.bit.rsvd = 0; // b13 , 0 Reserved
//EvaRegs.T1CON.bit.TMODE = 1; // b12-b11, 01->Continuous up/down count mode
//EvaRegs.T1CON.bit.TPS = 0; // b10-b8 ,000->Clock prescaler x/1
//EvaRegs.T1CON.bit.rsvd2 = 0; // b7 , 0 Reserved
//EvaRegs.T1CON.bit.TENABLE = 1; // b6 , 1->Timer1 enable
//EvaRegs.T1CON.bit.TCLKS10 = 0; // b5-b4 , 00->Clock Source: internal (HSPCLK)
//EvaRegs.T1CON.bit.TCLD10 = 0; // b3-b2 , 01->Timer compare reg reload T1CNT is 0 (Underflow) and T1PR (Period)
//EvaRegs.T1CON.bit.TECMPR = 1; // b1 , 1->Timer compare enable
//EvaRegs.T1CON.bit.rsvd1 = 0; // b0 , 0->Reserved
// Setup EVA-T2,
//-----------------------------------------------------------------------
// Not used now
// Initialize EVA Timer 2:
// Setup Timer 2 Registers (EV A)
EvaRegs.T2CNT = 0x0000; // Clear counter
EvaRegs.T2PR = 0xFFFF; // Max T2 period
EvaRegs.T2CMPR = 0x0000; // Not used
EvaRegs.T2CON.all = 0x1870; // Timer is used for Speed Encoder
// Directional Up/Down, QEP as clock source, Timer Enable
//EvaRegs.T2CON.bit.SOFT = 0; // b15 , 0->
//EvaRegs.T2CON.bit.FREE = 0; // b14 , 0->Stop immediately on emu. suspend
//EvaRegs.T2CON.bit.rsvd = 0; // b13 , 0 Reserved
//EvaRegs.T2CON.bit.TMODE = 3; // b12-b11, 11->Directional Up/Down Count Mode
//EvaRegs.T2CON.bit.TPS = 0; // b10-b8 ,000->No prescaler, x/1
//EvaRegs.T2CON.bit.T2SWT1 = 0; // b7 , 0->Use own enable bit
//EvaRegs.T2CON.bit.TENABLE = 1; // b6 , 0->Enable timer
//EvaRegs.T2CON.bit.TCLKS10 = 3; // b5-b4 , 11->QEP Clock
//EvaRegs.T2CON.bit.TCLD10 = 0; // b3-b2 , 00->T2CMPR reload when 0 (not used)
//EvaRegs.T2CON.bit.TECMPR = 0; // b1 , 1->Timer compare disabled
//EvaRegs.T2CON.bit.SET1PR = 0; // b0 , 0->Use own period register
EvaRegs.CAPCONA.all = 0x0000; // Disable captures
EvaRegs.EXTCONA.all = 0x0000;
//EvaRegs.EXTCONA.bit.EVSOCE = 0; // b3, 0->EVSOC output disabled
//EvaRegs.EXTCONA.bit.QEPIE = 0; // b2, 0->QEPI1 index input disabled
//EvaRegs.EXTCONA.bit.QEPIQUAL = 0; // b1, 0->QEPI1 index qualification off
//EvaRegs.EXTCONA.bit.INDCOE = 0; // b0, 0->Independent compare output disabled
EvaRegs.EVAIMRA.all = 0x0000; // Disable interrupts
//EvaRegs.EVAIMRA.rsvd2 = 0; // 15:11 reserved
//EvaRegs.EVAIMRA.T1OFINT = 0; // 10 Disable
//EvaRegs.EVAIMRA.T1UFINT = 0; // 9 Disable
//EvaRegs.EVAIMRA.T1CINT = 0; // 8 Disable
//EvaRegs.EVAIMRA.T1PINT = 1; // 7 Enable
//EvaRegs.EVAIMRA.rsvd1 = 0; // 6:4 reserved
//EvaRegs.EVAIMRA.CMP3INT = 0; // 3 Disable
//EvaRegs.EVAIMRA.CMP2INT = 0; // 2 Disable
//EvaRegs.EVAIMRA.CMP1INT = 0; // 1 Disable
//EvaRegs.EVAIMRA.PDPINTA = 0; // 0 Disable PDPINTA
EvaRegs.EVAIMRB.all = 0x0000; // Disable interrupts
EvaRegs.EVAIMRC.all = 0x0000; // Disable interrupts
EvaRegs.EVAIFRA.all = 0xFFFF; // Clear all pending interrupts
EvaRegs.EVAIFRB.all = 0xFFFF; // Clear all pending interrupts
EvaRegs.EVAIFRC.all = 0xFFFF; // Clear all pending interrupts
EvaRegs.EVAIMRA.bit.T1PINT = 0; // T1PINT int disabled
EvaRegs.EVAIFRA.bit.T1PINT = 1; // T1PINT int flag clear
/*
// Setup EVB-T3, timeBase 40ns (HSPCLK)
//-----------------------------------------------------------------------
// Not used
EvbRegs.T3PR = 0xFFFF; // 52.08us/40ns=1302 (useful for 19200 baud)
EvbRegs.T3CNT = 0x0000; // Clear counter
EvbRegs.CMPR4 = EvbRegs.T3PR; // (0V)
EvbRegs.CMPR5 = EvbRegs.T3PR; // (0V)
EvbRegs.CMPR6 = EvbRegs.T3PR; // (0V)
EvbRegs.T3CMPR= EvbRegs.T3PR; // (0V)
EvbRegs.GPTCONB.all = 0x004A;
//EvbRegs.GPTCONB.bit.rsvd2 =0; // b15 , 0 Reserved
//EvbRegs.GPTCONB.bit.T4STAT =0; // b14 , 0 GP Timer 4 status (Read only)
//EvbRegs.GPTCONB.bit.T3STAT =0; // b13 , 0 GP Timer 3 status (Read only)
//EvbRegs.GPTCONB.bit.T4CTRIPE =0; // b12 , 0->T4CTRIP disabled
//EvbRegs.GPTCONB.bit.T3CTRIPE =0; // b11 , 0->T3CTRIP disabled
//EvbRegs.GPTCONB.bit.T4TOADC =0; // b10-b9, 00->No T4 event starts ADC
//EvbRegs.GPTCONB.bit.T3TOADC =0; // b8-b7 , 00->No T3 event starts ADC
//EvbRegs.GPTCONB.bit.TCMPOE =1; // b6 , 1->Enable T3/T4 PWM/CMPR by compare logic. Bit active only if EXTCON(0)=0, otherwise reserved
//EvbRegs.GPTCONB.bit.T4CMPOE =0; // b5 , 0 Reserved if EXTCON(0) = 0.
//EvbRegs.GPTCONB.bit.T3CMPOE =0; // b4 , 0 Reserved if EXTCON(0) = 0.
//EvbRegs.GPTCONB.bit.T4PIN =2; // b3-b2 , 10->Active high, pol. of GP Timer 4 compare output
//EvbRegs.GPTCONB.bit.T3PIN =2; // b1-b0 , 10->Active high, pol. of GP Timer 3 compare output
EvbRegs.ACTRB.all = 0x0000; // Not used
//EvbRegs.ACTRB.bit.SVRDIR =0; // b15 , 0->Space vector PWM rotation
//EvbRegs.ACTRB.bit.D =0; // b14-b12, 0->Space vector bits
//EvbRegs.ACTRB.bit.CMP12ACT =0; // b11-b10,00->PWM12 Forced low
//EvbRegs.ACTRB.bit.CMP11ACT =2; // b9-b8 ,10->PWM11 Active high
//EvbRegs.ACTRB.bit.CMP10ACT =0; // b7-b6 ,00->PWM10 Forced low
//EvbRegs.ACTRB.bit.CMP9ACT =2; // b5-b4 ,10->PWM9 Active high
//EvbRegs.ACTRB.bit.CMP8ACT =0; // b3-b2 ,00->PWM8 Forced low
//EvbRegs.ACTRB.bit.CMP7ACT =2; // b1-b0 ,10->PWM7 Active high
EvbRegs.DBTCONB.all = 0x0000; // No dead-time
EvbRegs.COMCONB.all = 0x0000;
//EvbRegs.COMCONB.bit.CENABLE = 1; // b15 , 1->Compare enable
//EvbRegs.COMCONB.bit.CLD = 0; // b14-b13, 00->Compare reload when T3CNT is 0 (Underflow)
//EvbRegs.COMCONB.bit.SVENABLE = 0; // b12 , 0->Space vector PWM disabled
//EvbRegs.COMCONB.bit.ACTRLD = 0; // b11-b10, 00->ACTR reload when T3CNT is 0 (Underflow)
//EvbRegs.COMCONB.bit.FCOMPOE = 1; // b9 , 1->Full compare outputs enabled. Bit active only if EXTCON(0)=0, otherwise reserved
//EvbRegs.COMCONB.bit.PDPINTBSTATUS= 0; // b8, 0 PDPINTB status (Read only)
//EvbRegs.COMCONB.bit.FCMP6OE = 0; // b7 , 0 Reserved if EXTCON(0) = 0.
//EvbRegs.COMCONB.bit.FCMP5OE = 0; // b6 , 0 Reserved if EXTCON(0) = 0.
//EvbRegs.COMCONB.bit.FCMP4OE = 0; // b5 , 0 Reserved if EXTCON(0) = 0.
//EvbRegs.COMCONB.bit.rsvd = 0; // b4-b3 , 00 Reserved
//EvbRegs.COMCONB.bit.C6TRIPE = 0; // b2 , 0->C6TRIP disabled
//EvbRegs.COMCONB.bit.C5TRIPE = 0; // b1 , 0->C5TRIP disabled
//EvbRegs.COMCONB.bit.C4TRIPE = 0; // b0 , 0->C4TRIP disabled
EvbRegs.T3CON.all = 0x1042; // Continuous up, enable timer, enable compare, reload @0
//EvbRegs.T3CON.bit.FREE = 0; // b15 , 0->
//EvbRegs.T3CON.bit.SOFT = 0; // b14 , 0->Stop immediately on emulator suspned
//EvbRegs.T3CON.bit.rsvd = 0; // b13 , 0 Reserved
//EvbRegs.T3CON.bit.TMODE = 2; // b12-b11, 10->Continuous up/down count mode
//EvbRegs.T3CON.bit.TPS = 0; // b10-b8 ,000->Clock prescaler x/1
//EvbRegs.T3CON.bit.rsvd2 = 0; // b7 , 0 Reserved
//EvbRegs.T3CON.bit.TENABLE = 1; // b6 , 1->Timer1 enable
//EvbRegs.T3CON.bit.TCLKS10 = 0; // b5-b4 , 00->Clock Source: internal (HSPCLK)
//EvbRegs.T3CON.bit.TCLD10 = 0; // b3-b2 , 00->Timer compare regs reload when counter is 0
//EvbRegs.T3CON.bit.TECMPR = 1; // b1 , 1->Timer compare enable
//EvbRegs.T3CON.bit.rsvd1 = 0; // b0 , 0->Reserved
// Setup EVB-T4, timeBase 40ns (HSPCLK)
//-----------------------------------------------------------------------
// Used for SW_UART
EvbRegs.T4CNT = 0x0000; // Clear counter
EvbRegs.T4PR = 0x00FF; //
EvbRegs.T4CMPR = 0x0030;
EvbRegs.T4CON.all = 0x1042; // Continous up, enable timer, enable compare, reload @0
//EvbRegs.T4CON.bit.SOFT = 0; // b15 , 0->
//EvbRegs.T4CON.bit.FREE = 0; // b14 , 0->Stop immediately on emu. suspend
//EvbRegs.T4CON.bit.rsvd = 0; // b13 , 0 Reserved
//EvbRegs.T4CON.bit.TMODE = 2; // b12-b11, 10->Continuous up mode
//EvbRegs.T4CON.bit.TPS = 0; // b10-b8 ,000->No prescaler, x/1
//EvbRegs.T4CON.bit.T4SWT1 = 0; // b7 , 0->Use own enable bit
//EvbRegs.T4CON.bit.TENABLE = 1; // b6 , 1->Enable timer
//EvbRegs.T4CON.bit.TCLKS10 = 0; // b5-b4 , 00->Clock source=Internal (HSPCLK)
//EvbRegs.T4CON.bit.TCLD10 = 0; // b3-b2 , 00->T4CMPR reload when 0 (not used)
//EvbRegs.T4CON.bit.TECMPR = 1; // b1 , 1->Timer compare disabled
//EvbRegs.T4CON.bit.SET3PR = 0; // b0 , 0->Use own period register
EvbRegs.CAPCONB.all = 0x0000; // Disable captures
EvbRegs.EXTCONB.all = 0x0000;
//EvbRegs.EXTCONB.bit.EVSOCE = 0; // b3, 0->EVSOC output disabled
//EvbRegs.EXTCONB.bit.QEPIE = 0; // b2, 0->QEPI12 index input disabled
//EvbRegs.EXTCONB.bit.QEPIQUAL = 0; // b1, 0->QEPI12 index qualification off
//EvbRegs.EXTCONB.bit.INDCOE = 0; // b0, 0->Independent compare output disabled
EvbRegs.EVBIMRA.all = 0x0000; // Disable interrupts
EvbRegs.EVBIMRB.all = 0x0000; // Disable interrupts
EvbRegs.EVBIMRC.all = 0x0000; // Disable interrupts
EvbRegs.EVBIFRA.all = 0xFFFF; // Clear all pending interrupts
EvbRegs.EVBIFRB.all = 0xFFFF; // Clear all pending interrupts
EvbRegs.EVBIFRC.all = 0xFFFF; // Clear all pending interrupts
EvbRegs.EVBIMRB.bit.T4PINT = 1; // T4PINT int enable
*/
}
//---------------------------------------------------------------------------
// ADC:
//---------------------------------------------------------------------------
void InitAdc(void)
{
// To powerup the ADC the ADCENCLK bit should be set first to enable
// clocks, followed by powering up the bandgap and reference circuitry.
// After a 5ms delay the rest of the ADC can be powered up. After ADC
// powerup, another 20us delay is required before performing the first
// ADC conversion. Please note that for the delay function below to
// operate correctly the CPU_CLOCK_SPEED define statement in the
// DSP28_Examples.h file must contain the correct CPU clock period in
// nanoseconds. For example:
AdcRegs.ADCTRL3.bit.EXTREF = 1; // ADCREFP(2V) and ADCREFM(1V) pins are inputs for external reference voltages
// Note: Do not enable internal references when external references are connected to reference pins
AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3; // Power up bandgap/reference circuitry
DELAY_US(ADC_usDELAY); // 10ms delay before powering up rest of ADC as per datasheet pg no. 146
AdcRegs.ADCTRL3.bit.ADCPWDN = 1; // Power up rest of ADC
DELAY_US(ADC_usDELAY2); // 50us delay after powering up ADC as per datasheet pg no. 146
AdcRegs.ADCTRL3.bit.SMODE_SEL = 1; // Simultaneous sampling mode
// 0: sequential 1: simultaneous
AdcRegs.ADCTRL1.all = 0x3110; // EMU suspend immediately, clk/1 prescale, 1 clk SH (40ns), trigg run , cascaded
// AdcRegs.ADCTRL1.bit.RESET = 0; // b14 , 0->No effect
// AdcRegs.ADCTRL1.bit.SUSMOD = 3; // b13-b12, 3->EMU suspend immediately
// AdcRegs.ADCTRL1.bit.ACQ_PS = 1; // b11-b8 , 1->time duration for which the sampling switch is closed, tsh=(ACQ_PS+1)clk = 2*40ns = 80ns
// AdcRegs.ADCTRL1.bit.CPS = 0; // b7 , 0->Fclk=CLK/1 Core clock prescaler
// AdcRegs.ADCTRL1.bit.CONT_RUN = 0; // b6 , 0->Start-stop mode. Sequencer stops after reaching EOS. Sequencer starts
// AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0; // b5 , 0->Disabled − Allows the sequencer to wrap around at the end of conversions set by MAX CONVn.
// AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // b4 , 1->Cascaded mode
AdcRegs.ADCMAXCONV.all = 0x0007; // 8 double conversions are to be performed
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup conv from ADCINA0 & ADCINB0
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup conv from ADCINA1 & ADCINB1
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup conv from ADCINA2 & ADCINB2
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup conv from ADCINA3 & ADCINB3
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup conv from ADCINA4 & ADCINB4
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup conv from ADCINA5 & ADCINB5
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup conv from ADCINA6 & ADCINB6
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup conv from ADCINA7 & ADCINB7
AdcRegs.ADCTRL2.bit.EVA_SOC_SEQ1= 1; // bit 8 , 1->Allows SEQ1/SEQ to be started by Event Manager A trigger
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1= 1; // bit 11, 1->Interrupt request by INT SEQ1 is enabled
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1= 0; // bit 10, 0->INT SEQ1 is set at the end of every SEQ1 sequence
AdcRegs.ADCTRL3.bit.ADCCLKPS = 2; // Sys clk = 150MHz, HISPCLK = SYSCLK/6 => ADC clk in = 25MHz. ADCCLKPS = 2 => FCLK = 25/(2*ADCCLKPS) = 6.25MHz < 25MHz
}
//---------------------------------------------------------------------------
// Flash Initialization:
//---------------------------------------------------------------------------
void InitFlash(void)
{
EALLOW;
//Enable Flash Pipeline mode to improve performance
//of code executed from Flash.
FlashRegs.FOPT.bit.ENPIPE = 1;
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
// CAUTION
//Minimum cycles required to move between power states
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
//Set Flash in Active state (No low power mode)
FlashRegs.FPWR.bit.PWR=0x0003;
//For now use the default count
//Set number of cycles to transition from sleep to standby
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
//Set number of cycles to transition from standby to active
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
{
while(SourceAddr < SourceEndAddr)
{
*DestAddr++ = *SourceAddr++;
}
return;
}
//===========================================================================
// No more.
//===========================================================================
Ozino,
Yes I updated linker command file and codestartbranch.asm files with the DSP28xxx version. Right now as I mentioned before it is running fine but the procedure for debugging is too long. I dunno why it is so complex.
Thanks!
Kashyap
Hi Sal,
Following are the two procedures I followed:
1) Initially I was using Memcpy() function to copy selected CODE SECTIONS from Flash to RAM during initialization after entering main(). But I wanted to copy all the code from Flash to RAM.
2) I have followed the procedure given in SPRAAU8 to copy all the code from flash to RAM at the time of booting. I didn't get any build errors after that.
In the first case, once the program is loaded into the DSP, cursor enters main and stops there. I can press the RUN button after that and can debug without any issue.
In the second case, once the program is loaded into DSP, cursor was not entering main(). I had to disconnect and restart the controller (by powering it OFF and ON). When I reconnect and load the same program it is entering the main() and then it is running properly. So, the problem in the second case is for every small change I had to load the program, disconnect, restart, re-connect and load the same program again to debug using JTAG, which is becoming very long process. I am not sure why it is happening like this. If you can suggest an alternative, it would be very helpful.
Thanks!
Kashyap
