F28M36P63C2: I2C write not working with C28 of F28m36x controller.

We don't have any examples specifically for the C28 side of the F28M36x, but you were correct in your use of one of the other C28 device's i2c_eeprom examples--aside from some possible changes in FIFO size, the I2C is the same.

Just to clarify, the clock does toggle while the slave address is being sent--it just stays low afterward, correct? It sounds like maybe it's what is described under "Hardware Response to a NACK" on this page. Can you check the status bits in I2CSTR and try what that page recommends for NACK handling?

Whitney

Yes based on that wiki link I'm checking the ARDY status bit in I2CSTR, set and cleared STP and NACK registers. Now my clock signal goes back to high. But still I can only see the Address byte and after that both the SDA and SCL stays high.

I'm trying to send the data based on FIFO transmit and I enabled it with the following setting.

I2caRegs.I2CFFTX.all = 0x6000;   // Enable FIFO mode and TXFIFO

My I2C init and I2C write are as follows:

void I2CA_Init(void)
{
I2caRegs.I2CSAR = 0x60; // Slave address of DAC

I2caRegs.I2CPSC.all = 14; //for CPU_FRQ_150MHZ, SYSCLK/(I2CPSC+1)

I2caRegs.I2CCLKL = 10; // NOTE: must be non zero
I2caRegs.I2CCLKH = 5; // NOTE: must be non zero
I2caRegs.I2CIER.all = 0x0; // Enable SCD & ARDY interrupts

I2caRegs.I2CMDR.all = 0x0020; // Take I2C out of reset

I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO

return;
}

void I2C_write_new()
{
Uint16 i = 0;
// Setup slave address
// I2caRegs.I2CSAR = 0x60;

while (I2caRegs.I2CSTR.bit.BB == 1)
{
i = 1;
}
I2caRegs.I2CCNT = 3;

I2caRegs.I2CDXR = 0x60;
I2caRegs.I2CDXR = 0x66;
I2caRegs.I2CDXR = 0x60;

I2caRegs.I2CMDR.bit.TRX = 1; //Set to Transmit mode
I2caRegs.I2CMDR.bit.STP = 1; //Master must release bus once Tx is complete , i.e. I2CCNT =0
I2caRegs.I2CMDR.bit.MST = 1; //Set to Master mode
I2caRegs.I2CMDR.bit.FREE = 1; //Debugger will not halt the bus on a breakpoint
I2caRegs.I2CMDR.bit.STT = 1; //Send the start bit, transmission will follow
// Send start as master transmitter
// I2caRegs.I2CMDR.all = 0x6E20;

while(!(I2caRegs.I2CSTR.bit.ARDY));

if(I2caRegs.I2CSTR.bit.NACK)
{
I2caRegs.I2CMDR.bit.STP = 1;
I2caRegs.I2CSTR.bit.NACK = 1;
}

}

I'm trying to send 3 bytes of data and the data is given to I2CDXR, Are there any other register setting required for a FIFO data send?

Thanks

Your FIFO setup seems okay. As you step through your writes to I2CDXR, do you see the FIFO level status in I2CFFTX increasing? After you run the rest of the code, do you see it go back to 0? What about I2CCNT? Does it return to 0 after you run the code?

Whitney

Yes the TXFFST in I2CFFTX increases to 3 as I step through I2CDXR writes. I2CCNT goes to 3 too. But both the registers stay at 3 even after i2c start send "I2caRegs.I2CMDR.bit.STT = 1;".

I2CFFTX status-->

I2CSTR status-->

Hello Whitney,

I removed the FIFO send code and trying to send 3 bytes of data by polling the XRDY register. After "I2caRegs.I2CMDR.bit.STT = 1;" is executed I'm polling for the XRDY register and sending data. Initially the XRDY is 1 and after I send the 1st byte of data, it is set to 0 and never resets to 1 and I don't see any data after the address byte on the scope. 

According to the TRM when XRDY is 1 "I2CDXR ready: Data has been copied from I2CDXR to I2CXSR" so after I give my data to I2CDXR, internally it is not sent to I2CXSR to make the XRDY 1. (page 1229)

Only when XRDY is 1 I can send my 2nd byte of data and can assume that my 1st byte is sent successfully. The code snippet to I2C write is as follows:

void I2C_write_new_nofifo()
{
    Uint16 i = 0;
    // Setup slave address
    I2caRegs.I2CSAR = 0x60;

    I2caRegs.I2CCNT = 3;
    I2caRegs.I2CMDR.bit.TRX = 1;                 //Set to Transmit mode
    I2caRegs.I2CMDR.bit.STP = 1;                //Master must release bus once Tx is complete , i.e. I2CCNT =0
    I2caRegs.I2CMDR.bit.MST = 1;                //Set to Master mode
    I2caRegs.I2CMDR.bit.FREE = 1;              //Debugger will not halt the bus on a breakpoint
    I2caRegs.I2CMDR.bit.STT = 1;                 //Send the start bit, transmission will follow


    for(i=0; i<3 ;i++)
    {
        while(I2caRegs.I2CSTR.bit.XRDY == 0){}; //Do nothing till bus is free
        I2caRegs.I2CDXR = (unsigned int)ulDataTx[i]; //Next data byte
    }

}

My I2C init is as follows:

void I2CA_Init(void)
{
    I2caRegs.I2CPSC.all = 14; //for CPU_FRQ_150MHZ, SYSCLK/(I2CPSC+1)

    I2caRegs.I2CCLKL = 45;           // NOTE: must be non zero//SCL 100khz
    I2caRegs.I2CCLKH = 45;            // NOTE: must be non zero
    I2caRegs.I2CIER.all = 0x0;      // Enable SCD & ARDY interrupts

    I2caRegs.I2CMDR.all = 0x0020;    // Take I2C out of reset
    return;
}

Is there any register setting which is missing to shift the data from I2CDXR ->  I2CXSR?

The I2CCNT remains as 3 and is not decremented.

status register is as follows:

Karthik

Yes I resolved the issue the DAC ACK is not received due to a digital isolator in between. This hardware setup worked without any issues with M3, and the c28 do not send the next byte without ACK. Is there any way for my C28 to ignore the ACK bit and continue sending the data bytes?

Thanks