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Hi,
I had asked F280049 SDFM example before one year.
https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/699474/2578448
And still not release in latest c2000ware.
Does TI release it now?
I have some troubles with using SDFM on F280049.
thanks,
best regards,
Simen
Manoj,
I use F2838x SDFM example and modify it to fit F280049. (F2838x_sdfm_ex4_pwm_sync_cpuread.c)
When the program execute run .
It does not enter SDFM ISR and get data.
But just pause the program and go on running again.
It can run correctly and get the right data.
I have no idea why .
attach my code , SDFM register value ,and use AMC1305M25 EVM
----------------------------------------------------------------------
//###########################################################################
//
// FILE: sdfm_ex4_pwm_sync_cpuread.c
//
// TITLE: SDFM PWM Sync Example
//
//! \addtogroup driver_example_list
//! <h1> SDFM PWM Sync </h1>
//!
//! In this example, SDFM filter data is read by CPU in SDFM ISR routine. The
//! SDFM configuration is shown below:
//! - SDFM1 is used in this example. For using SDFM2, few modifications
//! would be needed in the example.
//! - MODE0 Input control mode selected
//! - Comparator settings
//! - Sinc3 filter selected
//! - OSR = 32
//! - hlt = 0x7FFF (Higher threshold setting)
//! - llt = 0x0000(Lower threshold setting)
//! - Data filter settings
//! - All the 4 filter modules enabled
//! - Sinc3 filter selected
//! - OSR = 256
//! - All the 4 filters are synchronized by using PWM
//! (Master Filter enable bit)
//! - Filter output represented in 16 bit format
//! - In order to convert 25 bit Data filter
//! into 16 bit format user needs to right shift by 10 bits for
//! Sinc3 filter with OSR = 256
//! - Interrupt module settings for SDFM filter
//! - All the 4 higher threshold comparator interrupts disabled
//! - All the 4 lower threshold comparator interrupts disabled
//! - All the 4 modulator failure interrupts disabled
//! - All the 4 filter will generate interrupt when a new filter data
//! is available
//!
//! \b External \b Connections \n
//! - SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to
//! (SD-D1, SD-C1 to SD-D8,SD-C8) on GPIO16-GPIO31
//! - SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to
//! (SD-D1, SD-C1 to SD-D8,SD-C8) on GPIO48-GPIO63
//! - SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to
//! (SD-D1, SD-C1 to SD-D8,SD-C8) on GPIO122-GPIO137
//!
//! \b Watch \b Variables \n
//! - \b filter1Result - Output of filter 1
//! - \b filter2Result - Output of filter 2
//! - \b filter3Result - Output of filter 3
//! - \b filter4Result - Output of filter 4
//!
//
//###########################################################################
// 20190722(sdfm_ex4_pwm_sync_cpuread_bsp002.c) ePWM2 for AM1305 CLK, SDFM ISR ok
// 20190722(sdfm_ex4_pwm_sync_cpuread_bsp005.c) SDFM ISR bug.
//###########################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include <stdio.h>
//
// Defines
//
#define MAX_SAMPLES 1024
#define SDFM_PIN_MUX_OPTION1 1
#define SDFM_PIN_MUX_OPTION2 2
#define SDFM_PIN_MUX_OPTION3 3
#define EPWM_TIMER_TBPRD 65535 // ePWM Period register
#define SDFM_INT_MASK 0x8000F000U
//
// Macro to read the SDFM filter data in 16-bit format
//
#define READ_16BIT_FILTER_DATA(base, offset) \
(*((volatile int16_t *)(base + offset + 1)))
#define READ_32BIT_FILTER_DATA(base, offset) \
(*((volatile int32_t *)(base + offset)))
//
// Globals
//
uint32_t sdfmInstance;
uint32_t pwmInstance = EPWM1_BASE; // ePWM 11 for synchronizing SDFM1 filters
int16_t filter1Result[MAX_SAMPLES];
int16_t filter2Result[MAX_SAMPLES];
int16_t filter3Result[MAX_SAMPLES];
int16_t filter4Result[MAX_SAMPLES];
#pragma DATA_SECTION(filter1Result, "Filter1_RegsFile");
//#pragma DATA_SECTION(filter2Result, "Filter2_RegsFile");
//#pragma DATA_SECTION(filter3Result, "Filter3_RegsFile");
//#pragma DATA_SECTION(filter4Result, "Filter4_RegsFile");
//
// Function Prototypes
//
//void configureSDFMPins(uint16_t sdfmPinOption);
//void setPinConfig1(void);
void initEPWM1(void);
void initEPWM2(void);
__interrupt void sdfm1ISR(void);
//
// Main
//
void main(void)
{
//
// Initialize device clock and peripherals
//
Device_init();
//
// Setup GPIO by disabling pin locks and enabling pullups
//
Device_initGPIO();
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
Interrupt_register(INT_SDFM1, sdfm1ISR);
//
// Configure GPIO0/1 , GPIO2/3 and GPIO4/5 as ePWM1A/1B, ePWM2A/2B and
// ePWM3A/3B pins respectively
//
GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD);
GPIO_setPinConfig(GPIO_0_EPWM1A);
GPIO_setPadConfig(1, GPIO_PIN_TYPE_STD);
GPIO_setPinConfig(GPIO_1_EPWM1B);
GPIO_setPadConfig(2, GPIO_PIN_TYPE_STD);
GPIO_setPinConfig(GPIO_2_EPWM2A);
GPIO_setPadConfig(3, GPIO_PIN_TYPE_STD);
GPIO_setPinConfig(GPIO_3_EPWM2B);
//
// Enable SDFM1 amd SDFM2 interrupts
//
Interrupt_enable(INT_SDFM1);
//
// Configure SDFM type to 0 and see if data ack generated SDINT.
//
// SysCtl_configureType(SYSCTL_SDFMTYPE, 0, 1);
//
// Configure GPIO pins as SDFM pins
//
GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN);
GPIO_setMasterCore(16, GPIO_CORE_CPU1);
GPIO_setPadConfig(16, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN);
GPIO_setMasterCore(17, GPIO_CORE_CPU1);
GPIO_setPadConfig(17, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_16_SD_D1);
GPIO_setPinConfig(GPIO_17_SD_C1);
//
// Select SDFM1
//
sdfmInstance = SDFM1_BASE;
//
// Input Control Module:
// Configure Modulator Clock rate = Modulator data rate
//
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_1,
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
//
// Data filter Module
//
// Configure Data filter modules filter type, OSR value and
// enable / disable data filter
//
// SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
// SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
// SDFM_SHIFT_VALUE(0x000A)));
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
SDFM_SHIFT_VALUE(0x000A)));
//
// Enable Master filter bit: Unless this bit is set none of the filter modules
// can be enabled. All the filter modules are synchronized when master filter
// bit is enabled after individual filter modules are enabled.
//
SDFM_enableMasterFilter(sdfmInstance);
// SDFM_enableFilter(sdfmInstance,SDFM_FILTER_1);
//
// PWM11.CMPC, PWM11.CMPD signals can synchronize SDFM1 filters and
// PWM12.CMPC and PWM12.CMPD signals can synchronize SDFM2 filters. This
// option is being used in this example for SDFM1.
//
SDFM_setPWMSyncSource(sdfmInstance,SDFM_FILTER_1,SDFM_SYNC_PWM1_SOCA);
SDFM_enableWaitForSync(sdfmInstance,SDFM_FILTER_1);
// SDFM_clearWaitForSyncFlag(sdfmInstance,SDFM_FILTER_1);
// SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_1);
//
// Init EPWMs
//
// initEPWM(pwmInstance);
//
// Disable sync(Freeze clock to PWM as well)
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
initEPWM1();
initEPWM2();
//
// Enable sync and clock to PWM
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//
// Enable interrupts
//
// Following SDFM interrupts can be enabled / disabled using this function.
// Enable / disable comparator high threshold
// Enable / disable comparator low threshold
// Enable / disable modulator clock failure
// Enable / disable filter acknowledge
//
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_1,
(SDFM_MODULATOR_FAILURE_INTERRUPT |
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_1,
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
// while((HWREGH(pwmInstance + EPWM_O_TBCTR)) < 550);
//----------------------------------------
SysCtl_delay(800000); //8ms, 2000 cycle (1 cycle=10 ns)
// SysCtl_delay(100000000); //1000ms, 2000 cycle (1 cycle=10 ns)
// SDFM_disableWaitForSync(sdfmInstance,SDFM_FILTER_1);
// SysCtl_delay(2000); //20us, 2000 cycle (1 cycle=10 ns)
SDFM_disableWaitForSync(sdfmInstance,SDFM_FILTER_1);
//-----------------------------------------
//
// Enable master interrupt so that any of the filter interrupts can trigger
// by SDFM interrupt to CPU
//
// SDFM_clearInterruptFlag(SDFM1_BASE, SDFM_INT_MASK);
//
// Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
SDFM_enableMasterInterrupt(sdfmInstance);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
while(1)
{
// GPIO_writePin(16,1);
// GPIO_writePin(17,1);
// SysCtl_delay(10000); //10000 cycle (1 cycle=10 ns)
// GPIO_writePin(16,0);
// GPIO_writePin(17,0);
// SysCtl_delay(10000); //10000 cycle (1 cycle=10 ns)
}
}
//
// sdfm1ISR - SDFM 1 ISR
//
__interrupt void sdfm1ISR(void)
{
static uint16_t loopCounter1 = 0;
//
// Wait for result from all the filters (SDIFLG)
//
while(HWREG(SDFM1_BASE + SDFM_O_SDIFLG) & SDFM_INT_MASK != SDFM_INT_MASK);
if(loopCounter1 <= MAX_SAMPLES)
{
//
// Read each SDFM filter output and store it in respective filter
// result array
//
filter1Result[loopCounter1++] =
READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA1);
// filter2Result[loopCounter1] =
// READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA2);
// filter3Result[loopCounter1] =
// READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA3);
// filter4Result[loopCounter1++] =
// READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA4);
}
else
{
loopCounter1 = 0;
}
//
// Clear SDFM flag register
//
SDFM_clearInterruptFlag(SDFM1_BASE, SDFM_INT_MASK);
//
// Acknowledge this __interrupt to receive more __interrupts from group 5
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
}
//
// done - Function to halt debugger and stop application
//
void done(void)
{
asm(" ESTOP0");
for(;;);
}
//
// initEPWM2 - Configure ePWM2
//
#define EPWM2_TIMER_TBPRD 50
void initEPWM2()
{
//
// Set-up TBCLK
//
EPWM_setTimeBasePeriod(EPWM2_BASE, EPWM2_TIMER_TBPRD);
EPWM_setPhaseShift(EPWM2_BASE, 0U);
EPWM_setTimeBaseCounter(EPWM2_BASE, 0U);
//
// Set Compare values
//
// EPWM_setCounterCompareValue(EPWM2_BASE,
// EPWM_COUNTER_COMPARE_A,
// EPWM2_MIN_CMPA);
// EPWM_setCounterCompareValue(EPWM2_BASE,
// EPWM_COUNTER_COMPARE_B,
// EPWM2_MIN_CMPB);
//
// Set-up counter mode
//
EPWM_setTimeBaseCounterMode(EPWM2_BASE, EPWM_COUNTER_MODE_UP_DOWN);
EPWM_disablePhaseShiftLoad(EPWM2_BASE);
EPWM_setClockPrescaler(EPWM2_BASE,
EPWM_CLOCK_DIVIDER_1,
EPWM_HSCLOCK_DIVIDER_1);
//
// Set-up shadowing
//
EPWM_setCounterCompareShadowLoadMode(EPWM2_BASE,
EPWM_COUNTER_COMPARE_A,
EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareShadowLoadMode(EPWM2_BASE,
EPWM_COUNTER_COMPARE_B,
EPWM_COMP_LOAD_ON_CNTR_ZERO);
//
// Set Action qualifier
//
EPWM_setActionQualifierAction(EPWM2_BASE,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(EPWM2_BASE,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(EPWM2_BASE,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(EPWM2_BASE,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
//
// Interrupt where we will change the Compare Values
// Select INT on Time base counter zero event,
// Enable INT, generate INT on 3rd event
//
// EPWM_setInterruptSource(EPWM2_BASE, EPWM_INT_TBCTR_ZERO);
// EPWM_enableInterrupt(EPWM2_BASE);
// EPWM_disableInterrupt(EPWM2_BASE);
// EPWM_setInterruptEventCount(EPWM2_BASE, 3U);
}
#define EPWM1_TIMER_TBPRD 1000
void initEPWM1()
{
//
// Set-up TBCLK
//
EPWM_setTimeBasePeriod(EPWM1_BASE, EPWM1_TIMER_TBPRD);
EPWM_setPhaseShift(EPWM1_BASE, 0U);
EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
//
// Set Compare values
//
EPWM_setCounterCompareValue(EPWM1_BASE,
EPWM_COUNTER_COMPARE_A,
300);
EPWM_setCounterCompareValue(EPWM1_BASE,
EPWM_COUNTER_COMPARE_B,
800);
//
// Set-up counter mode
//
EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);
EPWM_disablePhaseShiftLoad(EPWM1_BASE);
EPWM_setClockPrescaler(EPWM1_BASE,
EPWM_CLOCK_DIVIDER_1,
EPWM_HSCLOCK_DIVIDER_1);
//
// Set-up shadowing
//
EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE,
EPWM_COUNTER_COMPARE_A,
EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE,
EPWM_COUNTER_COMPARE_B,
EPWM_COMP_LOAD_ON_CNTR_ZERO);
//
// Set actions
//
EPWM_setActionQualifierAction(EPWM1_BASE,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(EPWM1_BASE,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(EPWM1_BASE,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(EPWM1_BASE,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
//
// Disable SOCA
//
EPWM_disableADCTrigger(EPWM1_BASE, EPWM_SOC_A);
//
// Configure the SOC to occur on the first up-count event
//
EPWM_setADCTriggerSource(EPWM1_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPA);
EPWM_setADCTriggerEventPrescale(EPWM1_BASE, EPWM_SOC_A, 1);
EPWM_enableADCTrigger(EPWM1_BASE, EPWM_SOC_A);
}
//
// End of file
//
521177 40 R Sdfm1Regs_SDIFLG 0x0000000B 0x80000100 R Sdfm1Regs_SDIFLGCLR 0x0000000B 0x00000000 R Sdfm1Regs_SDCTL 0x0000000F 0x2000 R Sdfm1Regs_SDMFILEN 0x0000000F 0x0800 R Sdfm1Regs_SDSTATUS 0x0000000F 0x0000 R Sdfm1Regs_SDCTLPARM1 0x0000000F 0x0000 R Sdfm1Regs_SDDFPARM1 0x0000000F 0x0FFF R Sdfm1Regs_SDDPARM1 0x0000000F 0x5000 R Sdfm1Regs_SDCMPH1 0x0000000F 0x7FFF R Sdfm1Regs_SDCMPL1 0x0000000F 0x0000 R Sdfm1Regs_SDCPARM1 0x0000000F 0x0200 R Sdfm1Regs_SDDATA1 0x0000000B 0xC1000000 R Sdfm1Regs_SDDATFIFO1 0x0000000B 0x00000000 R Sdfm1Regs_SDCDATA1 0x0000000F 0x0000 R Sdfm1Regs_SDCMPHZ1 0x0000000F 0x0000 R Sdfm1Regs_SDFIFOCTL1 0x0000000F 0x0000 R Sdfm1Regs_SDSYNC1 0x0000000F 0x0440 R Sdfm1Regs_SDCTLPARM2 0x0000000F 0x0000 R Sdfm1Regs_SDDFPARM2 0x0000000F 0x0000 R Sdfm1Regs_SDDPARM2 0x0000000F 0x0000 R Sdfm1Regs_SDCMPH2 0x0000000F 0x7FFF R Sdfm1Regs_SDCMPL2 0x0000000F 0x0000 R Sdfm1Regs_SDCPARM2 0x0000000F 0x0000 R Sdfm1Regs_SDDATA2 0x0000000B 0x00000000 R Sdfm1Regs_SDDATFIFO2 0x0000000B 0x00000000 R Sdfm1Regs_SDCDATA2 0x0000000F 0x0000 R Sdfm1Regs_SDCMPHZ2 0x0000000F 0x0000 R Sdfm1Regs_SDFIFOCTL2 0x0000000F 0x0000 R Sdfm1Regs_SDSYNC2 0x0000000F 0x0400 R Sdfm1Regs_SDCTLPARM3 0x0000000F 0x0000 R Sdfm1Regs_SDDFPARM3 0x0000000F 0x0000 R Sdfm1Regs_SDDPARM3 0x0000000F 0x0000 R Sdfm1Regs_SDCMPH3 0x0000000F 0x7FFF R Sdfm1Regs_SDCMPL3 0x0000000F 0x0000 R Sdfm1Regs_SDCPARM3 0x0000000F 0x0000 R Sdfm1Regs_SDDATA3 0x0000000B 0x00000000 R Sdfm1Regs_SDDATFIFO3 0x0000000B 0x00000000 R Sdfm1Regs_SDCDATA3 0x0000000F 0x0000 R Sdfm1Regs_SDCMPHZ3 0x0000000F 0x0000 R Sdfm1Regs_SDFIFOCTL3 0x0000000F 0x0000 R Sdfm1Regs_SDSYNC3 0x0000000F 0x0400 R Sdfm1Regs_SDCTLPARM4 0x0000000F 0x0000 R Sdfm1Regs_SDDFPARM4 0x0000000F 0x0000 R Sdfm1Regs_SDDPARM4 0x0000000F 0x0000 R Sdfm1Regs_SDCMPH4 0x0000000F 0x7FFF R Sdfm1Regs_SDCMPL4 0x0000000F 0x0000 R Sdfm1Regs_SDCPARM4 0x0000000F 0x0000 R Sdfm1Regs_SDDATA4 0x0000000B 0x00000000 R Sdfm1Regs_SDDATFIFO4 0x0000000B 0x00000000 R Sdfm1Regs_SDCDATA4 0x0000000F 0x0000 R Sdfm1Regs_SDCMPHZ4 0x0000000F 0x0000 R Sdfm1Regs_SDFIFOCTL4 0x0000000F 0x0000 R Sdfm1Regs_SDSYNC4 0x0000000F 0x0400
best regards,
Simen
Manoj,
Any update?
Does your software team finish the F280049 SDFM example code?
thanks,
best regards,
Simen
Simen,
I’m currently held up with some urgent project which I need to complete by end of this week. I can look into your issue early next week. Please expect a response by Monday / Tuesday next week.
Regards,
Manoj
Manoj,
I have found out the solution.
Because F28388D example code has "SysCtl_configureType(SYSCTL_SDFMTYPE, 0, 1)" function.
But F280049 does not have this function.
I have added the below code into my program and it works.
EALLOW;
HWREGH(DEVCFG_BASE + SYSCTL_O_SDFMTYPE) = (config | ((lock << SYSCTL_TYPE_LOCK_S) & SYSCTL_SDFMTYPE_LOCK));
EDIS;
best regards,
Simen