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Original question:

F28335 IER and PIEIER registers

TMS320F28027: IER & PIEIER RESET Problem

GUOOO
Prodigy 140 points

Part Number: TMS320F28027

Several paper of TI said: The cpu would clear the IER when it acknowledges a interrupt.

for example: paper TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual SPRUI09   Page142  1.6.3.3  Step7 "The CPU recognizes the interrupt and performs the automatic context save, clears the IER bit, sets INTM, and clears EALLOW."

But I do not reset the IER or PIEIER at ISR, and the interrupt operates normally. So I wonder the IER and PIEIER must be RESET by user? OR IER/PIEIER would be clear automaticaly by CPU/PIE  when come into a ISR ?

  • 0
    TI__Genius 10845 points

    Hi,

    The CPU does the automatic context saving of critical registers like IER, DP etc and also disables the global interrupts before entering the ISR. Once the ISR execution completes,  automatic context restore is done as well and hence there is no need to make any explicit change for setting the IER bit or INTM bit.

    Refer to cpu guide for more details on interrupt handling.

    Thanks

    Vasudha

  • 0 in reply to Vasudha Bhadoria
    TI__Genius 17315 points

    User5815340,

    When servicing an interrupt, the core IFR is automatically cleared by the CPU and the PIEIFR is manually cleared by the PieCtrlRegs.PIEACK.all = PIEACK_GROUPx; (where x is the group number) structure in the ISR.  For more information, please see the F28027 workshop at:

    https://training.ti.com/c2000-f2802x-microcontroller-workshop?cu=1137791

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • 0 in reply to Ken Schachter
    Prodigy 140 points

    Hi Ken,

    I wonder what the IER & PIEIER would do when servicing an interrupt, not the IFR&PIEIFR.

    THANKS!

  • 0 in reply to Vasudha Bhadoria
    Prodigy 140 points

    Hi Vasudha,

    So,  you mean the IER would be clear and INTM would be set by CPU automatically when coming into an interrupt. And then, when the ISR execution completes, the CPU would set the IER and clear the INTM automatically?

    And, user could not reset the IER and clear INTM in ISR? (in so many cases, the user only clear INTM but make no-action to IER)

  • 0 in reply to GUOOO
    TI__Genius 10845 points

    user5815340 said:
    So,  you mean the IER would be clear and INTM would be set by CPU automatically when coming into an interrupt. And then, when the ISR execution completes, the CPU would set the IER and clear the INTM automatically?

    Yes, the IER bit for thnterrupt which is getting serviced would be cleared ans the INTM would be set to disable interrupts globally. Once the ISR execution is completed, IER register which was stacked earler would be restored and the INTM would be cleared to enable interrupts globally. These details are available in cpu guide.

    cpu guide 

    user5815340 said:
    And, user could not reset the IER and clear INTM in ISR? (in so many cases, the user only clear INTM but make no-action to IER)

    User can update the IER register and clear the INTM bit to enable nesting of interrupts which is disabled by default. But once the ISR execution completes, IER register would be restored with the value which was configured before the interruot was serviced. Refer to interrupt nesting for steps to update IER and INTM inside ISR.

    Interrupt nesting

    Thanks

    Vasudha