LAUNCHXL-F28379D: Incorrect HR phase offset value for ePWM configured in up-down count mode

Aditya Padmanabha

Part Number: LAUNCHXL-F28379D

Hi,

I am facing issue setting the phase offset value for decimal values in HRPWM in up-down count mode. I have updated the example epwm_up_aq_cpu01 to perform the following settings.

1) Generate ePWM1 syncout to ePWM2

2) update phase value to TBPHS and TBPHSHR register for every sync event.

3) Use auto conversion to update mep_scale factor.

4) Use count up as the direction after phase update.

Code shown below.

for(;;)
{
EPwm2Regs.TBPHS.bit.TBPHS = (Uint16)phaseVal;

/*-- Update TBPHSHR --*/
float TBPHSf = phaseVal;
TBPHSf -= EPwm2Regs.TBPHS.bit.TBPHS;
TBPHSf *= 65536;
EPwm2Regs.TBPHS.bit.TBPHSHR = (Uint16)TBPHSf;
update_MepScaleFactor();
}

I have configured both ePWMs for 500KHz frequency and 50% duty cycle. I have attached the oscilloscope screenshots for 3 cases of phase values

Case 1: Phase offset - 7 clock cycles, expected value of phase delay - 50 ns, Actual phase delay - 50 ns (red), ePWM2(green) lags in phase compared to ePWM1(yellow)

Case 2: Phase offset - 8 clock cycles, expected value of phase delay - 60 ns, Actual phase delay - 60 ns, ePWM2 lags in phase compared to ePWM1

Case 3: Phase offset - 7.6 clock cycles, expected value of phase delay - 56 ns, Actual phase delay - 44 ns, ePWM2 lags in phase compared to ePWM1

I can see similar behavior for up count mode as well. Can you let us know if anything is missing here.

Attaching the source code

Fullscreen 2548.epwm_up_aq_cpu01.c Download

//###########################################################################
//
// FILE:   epwm_up_aq_cpu01.c
//
// TITLE:  Action Qualifier Module - Using up count.
//
//! \addtogroup cpu01_example_list
//! <h1> EPWM Action Qualifier (epwm_up_aq)</h1>
//!
//! This example configures ePWM1, ePWM2, ePWM3 to produce an
//! waveform with independent modulation on EPWMxA and
//! EPWMxB.
//!
//! The compare values CMPA and CMPB are modified within the ePWM's ISR.
//!
//! The TB counter is in up count mode for this example.
//!
//! View the EPWM1A/B(PA0_GPIO0 & PA1_GPIO1), EPWM2A/B(PA2_GPIO2 & PA3_GPIO3)
//! and EPWM3A/B(PA4_GPIO4 & PA5_GPIO5) waveforms via an oscilloscope.
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.06.00.00 $
// $Release Date: Mon May 27 06:48:24 CDT 2019 $
// $Copyright:
// Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include "SFO_V8.h"

//
// Defines
//
#define EPWM1_TIMER_TBPRD  2000  // Period register
#define EPWM1_MAX_CMPA     1950
#define EPWM1_MIN_CMPA       50
#define EPWM1_MAX_CMPB     1950
#define EPWM1_MIN_CMPB       50

#define EPWM2_TIMER_TBPRD  2000  // Period register
#define EPWM2_MAX_CMPA     1950
#define EPWM2_MIN_CMPA       50
#define EPWM2_MAX_CMPB     1950
#define EPWM2_MIN_CMPB       50

#define EPWM3_TIMER_TBPRD  2000  // Period register
#define EPWM3_MAX_CMPA      950
#define EPWM3_MIN_CMPA       50
#define EPWM3_MAX_CMPB     1950
#define EPWM3_MIN_CMPB     1050

#define EPWM_CMP_UP           1
#define EPWM_CMP_DOWN         0

//
// Globals
//
typedef struct
{
    volatile struct EPWM_REGS *EPwmRegHandle;
    Uint16 EPwm_CMPA_Direction;
    Uint16 EPwm_CMPB_Direction;
    Uint16 EPwmTimerIntCount;
    Uint16 EPwmMaxCMPA;
    Uint16 EPwmMinCMPA;
    Uint16 EPwmMaxCMPB;
    Uint16 EPwmMinCMPB;
}EPWM_INFO;

EPWM_INFO epwm1_info;
EPWM_INFO epwm2_info;
EPWM_INFO epwm3_info;

//
//  Function Prototypes
//
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void update_compare(EPWM_INFO*);

//
// Main
//


int MEP_ScaleFactor;
volatile struct EPWM_REGS *ePWM[] = { &EPwm1Regs, &EPwm2Regs, &EPwm3Regs,
  &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs, &EPwm9Regs,
  &EPwm10Regs, &EPwm11Regs, &EPwm12Regs };

void update_MepScaleFactor( void )
{
  /* MEP_ScaleFactor initialized using function SFO ()*/
  while (SFO() == 0) {
  }                /* MEP_ScaleFactor calculated by MEP Cal Module            */
}

float phaseVal = 7.5;
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
//    InitGpio();

//
// Enable PWM1, PWM2 and PWM3
//
    CpuSysRegs.PCLKCR2.bit.EPWM1=1;
    CpuSysRegs.PCLKCR2.bit.EPWM2=1;
    CpuSysRegs.PCLKCR2.bit.EPWM3=1;

//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
    InitEPwm1Gpio();
    InitEPwm2Gpio();
    InitEPwm3Gpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();

// For this example, only initialize the ePWM
//
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

    InitEPwm1Example();
    InitEPwm2Example();
    InitEPwm3Example();

    EALLOW;
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM

//
// Step 5. IDLE loop. Just sit and loop forever (optional):
//
    for(;;)
    {
        EPwm2Regs.TBPHS.bit.TBPHS = (Uint16)phaseVal;

        /*-- Update TBPHSHR --*/
          float TBPHSf = phaseVal;
          TBPHSf -= EPwm2Regs.TBPHS.bit.TBPHS;
          TBPHSf *= 65536;
          EPwm2Regs.TBPHS.bit.TBPHSHR = (Uint16)TBPHSf;
          update_MepScaleFactor();
    }
}

//
// InitEPwm1Example - Initialize EPWM1 values
//
void InitEPwm1Example()
{
   //
   // Setup TBCLK
   //
    EALLOW;

     // Time Base Control Register
      EPwm1Regs.TBCTL.bit.CTRMODE              = 2;          // Counter Mode
      EPwm1Regs.TBCTL.bit.SYNCOSEL             = 1;          // Sync Output Select
      EPwm1Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select
      EPwm1Regs.TBCTL.bit.PHSEN                = 0;          // Phase Load Enable
      EPwm1Regs.TBCTL.bit.PHSDIR               = 1;          // Phase Direction Bit
      EPwm1Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler
      EPwm1Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler
      EPwm1Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse

      /*-- Setup Time-Base (TB) Submodule --*/
      EPwm1Regs.TBPRD = 100;             // Time Base Period Register

      // Time-Base Phase Register
      EPwm1Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register

      // Time Base Counter Register
      EPwm1Regs.TBCTR = 0x0000;          /* Clear counter*/

      EPwm1Regs.CMPA.bit.CMPA = 50;     // Counter Compare A Register
      EPwm1Regs.CMPB.bit.CMPB = 50;     // Counter Compare B Register
      EPwm1Regs.CMPC = 32000;            // Counter Compare C Register
      EPwm1Regs.CMPD = 32000;            // Counter Compare D Register

      EPwm1Regs.AQCTLA.all = 82; // Action Qualifier Control Register For Output A
      EPwm1Regs.AQCTLB.all = 144;// Action Qualifier Control Register For Output B


      EPwm1Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control
      EPwm1Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control
      EPwm1Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control
      EPwm1Regs.DBCTL.bit.HALFCYCLE            = 1;          // Half Cycle Clocking Enable

      EPwm1Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options

      EPwm1Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A
      EPwm1Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B


      // Counter Compare Control Register
     EPwm1Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode
     EPwm1Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode
     EPwm1Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load
     EPwm1Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load


     EPwm1Regs.DBRED.bit.DBRED = 4;
                          // Dead-Band Generator Rising Edge Delay Count Register
     EPwm1Regs.DBFED.bit.DBFED = 4;
                         // Dead-Band Generator Falling Edge Delay Count Register

     EPwm1Regs.ETSEL.bit.SOCAEN               = 0;          // Start of Conversion A Enable
     EPwm1Regs.ETSEL.bit.SOCASELCMP = 0;
     EPwm1Regs.ETSEL.bit.SOCASEL              = 2 ;          // Start of Conversion A Select
     EPwm1Regs.ETPS.bit.SOCAPRD               = 3;          // EPWM1SOCA Period Select

     EPwm1Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable

     EPwm1Regs.ETSEL.bit.SOCBSELCMP = 0;
     EPwm1Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select
     EPwm1Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM1SOCB Period Select
     EPwm1Regs.ETSEL.bit.INTEN                = 0;          // EPWM1INTn Enable
     EPwm1Regs.ETSEL.bit.INTSELCMP = 0;
     EPwm1Regs.ETSEL.bit.INTSEL              = 1;          // Start of Conversion A Select

     EPwm1Regs.ETPS.bit.INTPRD                = 1;          // EPWM1INTn Period Select


     EPwm1Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit
     EPwm1Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit


     EPwm1Regs.EPWMXLINK.bit.TBPRDLINK = 0;
     EPwm1Regs.EPWMXLINK.bit.CMPALINK = 0;
     EPwm1Regs.EPWMXLINK.bit.CMPBLINK = 0;
     EPwm1Regs.EPWMXLINK.bit.CMPCLINK = 0;
     EPwm1Regs.EPWMXLINK.bit.CMPDLINK = 0;
     EDIS;
}

//
// InitEPwm2Example - Initialize EPWM2 values
//
void InitEPwm2Example()
{
    EALLOW;
    // Time Base Control Register
   EPwm2Regs.TBCTL.bit.CTRMODE              = 2;          // Counter Mode
   EPwm2Regs.TBCTL.bit.SYNCOSEL             = 0;          // Sync Output Select
   EPwm2Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select
   EPwm2Regs.TBCTL.bit.PHSEN                = 1;          // Phase Load Enable
   EPwm2Regs.TBCTL.bit.PHSDIR               = 1;          // Phase Direction Bit
   EPwm2Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler
   EPwm2Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler
   EPwm2Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse

   EPwm2Regs.TBPRD = 100;             // Time Base Period Register
   EPwm2Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register

   EPwm2Regs.TBCTR = 0x0000;          /* Clear counter*/

   // Counter Compare Control Register
   EPwm2Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode
   EPwm2Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode
   EPwm2Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load
   EPwm2Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load

   EPwm2Regs.CMPCTL2.bit.SHDWCMODE           = 0;  // Compare C Register Block Operating Mode

   EPwm2Regs.CMPCTL2.bit.SHDWDMODE           = 0;  // Compare D Register Block Operating Mode

   EPwm2Regs.CMPA.bit.CMPA = 50;     // Counter Compare A Register
   EPwm2Regs.CMPB.bit.CMPB = 50;     // Counter Compare B Register
   EPwm2Regs.CMPC = 32000;            // Counter Compare C Register
   EPwm2Regs.CMPD = 32000;            // Counter Compare D Register

   EPwm2Regs.AQCTLA.all = 82; // Action Qualifier Control Register For Output A
   EPwm2Regs.AQCTLB.all = 144;// Action Qualifier Control Register For Output B

   EPwm2Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A
   EPwm2Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B

   EPwm2Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options

   // Dead-Band Generator Control Register
   EPwm2Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control
   EPwm2Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control
   EPwm2Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control
   EPwm2Regs.DBCTL.bit.HALFCYCLE            = 1;          // Half Cycle Clocking Enable

   EPwm2Regs.DBRED.bit.DBRED = 4;
                        // Dead-Band Generator Rising Edge Delay Count Register
   EPwm2Regs.DBFED.bit.DBFED = 4;
                       // Dead-Band Generator Falling Edge Delay Count Register


   // Event Trigger Selection and Pre-Scale Register
  EPwm2Regs.ETSEL.bit.SOCAEN               = 0;          // Start of Conversion A Enable
  EPwm2Regs.ETSEL.bit.SOCASELCMP = 0;
  EPwm2Regs.ETSEL.bit.SOCASEL              = 2 ;          // Start of Conversion A Select
  EPwm2Regs.ETPS.bit.SOCAPRD               = 3;          // EPWM2SOCA Period Select

  EPwm2Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable

  EPwm2Regs.ETSEL.bit.SOCBSELCMP = 0;
  EPwm2Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select
  EPwm2Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM2SOCB Period Select
  EPwm2Regs.ETSEL.bit.INTEN                = 0;          // EPWM2INTn Enable
  EPwm2Regs.ETSEL.bit.INTSELCMP = 0;
  EPwm2Regs.ETSEL.bit.INTSEL              = 1;          // Start of Conversion A Select

  EPwm2Regs.ETPS.bit.INTPRD                = 1;          // EPWM2INTn Period Select

  // PWM Chopper Control Register
     EPwm2Regs.PCCTL.bit.CHPEN                = 0;          // PWM chopping enable
     EPwm2Regs.PCCTL.bit.CHPFREQ              = 0;          // Chopping clock frequency
     EPwm2Regs.PCCTL.bit.OSHTWTH              = 0;          // One-shot pulse width
     EPwm2Regs.PCCTL.bit.CHPDUTY              = 0;          // Chopping clock Duty cycle

     // HRPWM Configuration Register
    EPwm2Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit
    EPwm2Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit

    /* Update the Link Registers with the link value for all the Compare values and TBPRD */
    /* No error is thrown if the ePWM register exists in the model or not */
    EPwm2Regs.EPWMXLINK.bit.TBPRDLINK = 1;
    EPwm2Regs.EPWMXLINK.bit.CMPALINK = 1;
    EPwm2Regs.EPWMXLINK.bit.CMPBLINK = 1;
    EPwm2Regs.EPWMXLINK.bit.CMPCLINK = 1;
    EPwm2Regs.EPWMXLINK.bit.CMPDLINK = 1;

    /*-- Initial HRPWM for ePWM2 --*/

    EPwm2Regs.HRCNFG.all || 0x0;
    EPwm2Regs.HRCNFG.bit.EDGMODE = 3;
    EPwm2Regs.HRCNFG.bit.CTLMODE = 1;
    EPwm2Regs.HRCNFG.bit.HRLOAD = 1;
    EPwm2Regs.CMPA.bit.CMPAHR = 0;
    EPwm2Regs.TBPHS.bit.TBPHSHR = 1 << 8;
    EPwm2Regs.TBPRDHR = 0;
    EPwm2Regs.HRPCTL.bit.HRPE = 0;
    EPwm2Regs.HRCNFG.bit.AUTOCONV = 1;
    EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 0;
    EPwm2Regs.HRCNFG.bit.EDGMODEB = 3;
    EPwm2Regs.HRCNFG.bit.CTLMODEB = 0;
    EPwm2Regs.HRCNFG.bit.HRLOADB = 0;
    EPwm2Regs.CMPB.bit.CMPBHR = 0;
    EDIS;
    update_MepScaleFactor();
}

//
// InitEPwm3Example - Initialize EPWM3 values
//
void InitEPwm3Example(void)
{
   //
   // Setup TBCLK
   //
   EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
   EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD;       // Set timer period
   EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
   EPwm3Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
   EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

   //
   // Setup shadow register load on ZERO
   //
   EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   //
   // Set Compare values
   //
   EPwm3Regs.CMPA.bit.CMPA = EPWM3_MIN_CMPA;  // Set compare A value
   EPwm3Regs.CMPB.bit.CMPB = EPWM3_MAX_CMPB;  // Set Compare B value

   //
   // Set Actions
   //
   EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;         // Set PWM3A on event B, up count
   EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR;       // Clear PWM3A on event B,
                                              // up count
   EPwm3Regs.AQCTLB.bit.ZRO = AQ_TOGGLE;      // Toggle EPWM3B on Zero

   //
   // Interrupt where we will change the Compare Values
   //
   EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;  // Select INT on Zero event
   EPwm3Regs.ETSEL.bit.INTEN = 1;             // Enable INT
   EPwm3Regs.ETPS.bit.INTPRD = ET_3RD;        // Generate INT on 3rd event

   //
   // Start by increasing the compare A and decreasing compare B
   //
   epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP;
   epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN;

   //
   // Start the count at 0
   //
   epwm3_info.EPwmTimerIntCount = 0;
   epwm3_info.EPwmRegHandle = &EPwm3Regs;
   epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA;
   epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA;
   epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB;
   epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB;
}

//
// update_compare - Update the compare values for the specified EPWM
//
void update_compare(EPWM_INFO *epwm_info)
{
   //
   // Every 10'th interrupt, change the CMPA/CMPB values
   //
   if(epwm_info->EPwmTimerIntCount == 10)
   {
       epwm_info->EPwmTimerIntCount = 0;

       //
       // If we were increasing CMPA, check to see if
       // we reached the max value.  If not, increase CMPA
       // else, change directions and decrease CMPA
       //
       if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP)
       {
           if(epwm_info->EPwmRegHandle->CMPA.bit.CMPA < epwm_info->EPwmMaxCMPA)
           {
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA++;
           }
           else
           {
              epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN;
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA--;
           }
       }

       //
       // If we were decreasing CMPA, check to see if
       // we reached the min value.  If not, decrease CMPA
       // else, change directions and increase CMPA
       //
       else
       {
           if(epwm_info->EPwmRegHandle->CMPA.bit.CMPA == epwm_info->EPwmMinCMPA)
           {
              epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP;
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA++;
           }
           else
           {
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA--;
           }
       }

       //
       // If we were increasing CMPB, check to see if
       // we reached the max value.  If not, increase CMPB
       // else, change directions and decrease CMPB
       //
       if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP)
       {
           if(epwm_info->EPwmRegHandle->CMPB.bit.CMPB < epwm_info->EPwmMaxCMPB)
           {
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB++;
           }
           else
           {
              epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN;
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB--;
           }
       }

       //
       // If we were decreasing CMPB, check to see if
       // we reached the min value.  If not, decrease CMPB
       // else, change directions and increase CMPB
       //
       else
       {
           if(epwm_info->EPwmRegHandle->CMPB.bit.CMPB ==
              epwm_info->EPwmMinCMPB)
           {
              epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP;
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB++;
           }
           else
           {
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB--;
           }
       }
   }
   else
   {
      epwm_info->EPwmTimerIntCount++;
   }

   return;
}

//
// End of file
//

Thanks,

Aditya

over 6 years ago

0 Himanshu Chaudhary60 over 6 years ago

TI__Expert 3720 points

Hi,

The TBPHSHR configuration does not seem correct. I wonder if you have already enabled the auto-calibration feature of HRPWM then it makes sense to configure the entire 32-bit Phase register (both integral and fractional part) in one go by converting "phaseVal in Q16 fixed-point format" like this :

EPwm2Regs.TBPHS = (uint32_t)(phaseVal * (float32_t)((uint32_t)1 << 16) + 0.5f);

If my reply answers your question please click on "This resolved my issue" button located at the bottom of my post.

Regards

Himanshu

0 Aditya Padmanabha over 6 years ago in reply to Himanshu Chaudhary60

Expert 1440 points

Hi Himanshu,

Yes I have enabled auto-calibration feature.

EPwm2Regs.HRCNFG.bit.AUTOCONV = 1;

Configuring the entire 32-bit Phase register (both integral and fractional part) in one go by converting "phaseVal in Q16 fixed-point format" like this :

EPwm2Regs.TBPHS = (uint32_t)(phaseVal * (float32_t)((uint32_t)1 << 16) + 0.5f);

also does not help. I still see the same behaviour.

Thanks,

Aditya

0 Himanshu Chaudhary60 over 6 years ago in reply to Aditya Padmanabha

TI__Expert 3720 points

Hi,

Okay but I think you need to provide me more information because your initial question is not very clear.

You say "Case 1: Phase offset - 7 clock cycles, expected value of phase delay - 50 ns, Actual phase delay - 50 ns (red), ePWM2(green) lags in phase compared to ePWM1(yellow)"

But I think you meant expected delay to be 70ns as TBCLK is running at 100Mhz and also from the figure it seems Green leads the yellow one. So please revert with the correct information.

And also if you notice, in all the cases the expected - actual is 20ns (i.e. 2 clocks). I looked at your code, you have enable Rising Edge delay of 4 half TBCLK as well so I am guessing that might affect your measurements.

If my reply answers your question please click on "This resolved my issue" button located at the bottom of my post.

Regards

Himanshu

0 Aditya Padmanabha over 6 years ago in reply to Himanshu Chaudhary60

Expert 1440 points

Hi Himanshu,

That's expected delay of 2 clock cycles that happens due to the delay in loading the counter register. More details are provided in the e2e post

So I mention the expected delay as 50 ns considering the 2 clock cycles delay and thats what I measure actual value from CRO as well.

Thanks,

Aditya

0 Aditya Padmanabha over 6 years ago in reply to Aditya Padmanabha

Expert 1440 points

Hi,

Any updates on this issue?

Thanks,

Aditya

0 Himanshu Chaudhary60 over 6 years ago in reply to Aditya Padmanabha

TI__Expert 3720 points

Hi Aditya,

As we are already working on this issue offline, can we close this thread over here.

Thanks

Himanshu

0 Aditya Padmanabha over 6 years ago in reply to Himanshu Chaudhary60

Expert 1440 points

Hi Himanshu,

Sure. Thanks. Let me know when you have an update on this.

Thanks,

Aditya

C2000™︎ microcontrollers

C2000 microcontrollers forum

LAUNCHXL-F28379D: Incorrect HR phase offset value for ePWM configured in up-down count mode