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Compiler/LAUNCHXL-F28379D: Configuring ePWM interrupts

Lahiru Sandaruwan
Intellectual 270 points
Part Number: LAUNCHXL-F28379D
Other Parts Discussed in Thread: C2000WARE

Tool/software: TI C/C++ Compiler

Hi,

I'm trying to configure ePWM1 interrupts when CMPA value equals to TBCTR and oTBCTR increasing. I have written the following program and interrupts doesn't work. Please help me resolve the issue.

//Configuring interrupts
    asm(" SETC INTM, DBGM");            // Disable global interrupts

//--- Initialize the PIE_RAM.  There are:
//    32 base vectors + (12 PIE groups * 16 vectors/group) = 224 PIE vectors (448 words).
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;  // Disable the PIE
    asm(" EALLOW");                     // Enable EALLOW protected register access

    // Step around the first three 32-bit locations (six 16-bit locations).
    // These locations are used by the ROM bootloader during debug.
    memcpy((Uint16 *)&PieVectTable+6, (Uint16 *)&PieVectTableInit+6, 448-6);

    asm(" EDIS");                       // Disable EALLOW protected register access

//--- Disable all PIE interrupts
    PieCtrlRegs.PIEIER1.all =  0x0018; //Enable XINT1 & XINT 2
    PieCtrlRegs.PIEIER2.all =  0x0000;
    PieCtrlRegs.PIEIER3.all =  0x0FFF;  //Enable epwm interrupts
    PieCtrlRegs.PIEIER4.all =  0x0000;
    PieCtrlRegs.PIEIER5.all =  0x0000;
    PieCtrlRegs.PIEIER6.all =  0x0000;
    PieCtrlRegs.PIEIER7.all =  0x0000;
    PieCtrlRegs.PIEIER8.all =  0x0000;
    PieCtrlRegs.PIEIER9.all =  0x0000;
    PieCtrlRegs.PIEIER10.all = 0x0000;
    PieCtrlRegs.PIEIER11.all = 0x0000;
    PieCtrlRegs.PIEIER12.all = 0x0003; // Enable XINT 3 & 4

 PieCtrlRegs.PIEACK.all = 0xFFFF;

//--- Enable the PIE
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;      // Enable the PIE
    IER |= 0x0FFF;                          // Enable PIE Groups
    asm(" CLRC INTM, DBGM");

// Configuring ePWM
    asm(" EDIS");                       // Disable EALLOW protected register access
    asm(" EALLOW");                         // Enable EALLOW protected register access
    DevCfgRegs.SOFTPRES2.bit.EPWM1 = 1;     // ePWM2 is reset
    DevCfgRegs.SOFTPRES2.bit.EPWM1 = 0;     // ePWM2 is released from reset
    asm(" EDIS");                           // Disable EALLOW protected register access


    EPwm1Regs.TBCTL.bit.CTRMODE = 0x3;      // Disable the timer

    EPwm1Regs.TBCTL.all = 0xC033;           // Configure timer control register
    // bit 15-14     11:     FREE/SOFT, 11 = ignore emulation suspend
    // bit 13        0:      PHSDIR, 0 = count down after sync event
    // bit 12-10     100:    CLKDIV, 000 => TBCLK = HSPCLK/1
    // bit 9-7       000:    HSPCLKDIV, 000 => HSPCLK = EPWMCLK/1
    // bit 6         0:      SWFSYNC, 0 = no software sync produced
    // bit 5-4       11:     SYNCOSEL, 11 = sync-out disabled
    // bit 3         0:      PRDLD, 0 = reload PRD on counter=0
    // bit 2         0:      PHSEN, 0 = phase control disabled
    // bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)

    EPwm1Regs.TBCTR = 0x0000;               // Clear timer counter
    EPwm1Regs.TBPRD = 10000;    // Set timer period
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;     // Set timer phase

    EPwm1Regs.TBCTR = 0x0000;               // Clear timer counter

    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;     // Set timer phase

    EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x2;          // Compare control register
    EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x2;          // Compare control register

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;          // Compare control register
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;          // Compare control register

    EPwm1Regs.DBCTL.bit.OUT_MODE = 0;   // Deadband disabled
    EPwm1Regs.PCCTL.bit.CHPEN = 0;      // PWM chopper unit disabled
    EPwm1Regs.TZDCSEL.all = 0x0000;     // All trip zone and DC compare actions disabled

    EPwm1Regs.AQCTL.bit.LDAQAMODE = 0x0;
    EPwm1Regs.AQCTL.bit.LDAQBMODE = 0x0;
    EPwm1Regs.AQCTL.bit.SHDWAQAMODE = 0x1;
    EPwm1Regs.AQCTL.bit.SHDWAQBMODE = 0x1;
    EPwm1Regs.AQCTLA.bit.CAU = 0x0;
    EPwm1Regs.AQCTLA.bit.CAD = 0x0;
    EPwm1Regs.AQCTLA.bit.PRD = 0x0;
    EPwm1Regs.AQCTLA.bit.ZRO = 0x0;

    EPwm1Regs.ETPS.bit.INTCNT = 0x0;
    EPwm1Regs.ETPS.bit.INTPRD = 0x1;

    EPwm1Regs.ETSEL.bit.INTEN = 0x1;
    EPwm1Regs.ETSEL.bit.INTSEL = 0x5;
    EPwm1Regs.ETSEL.bit.INTSELCMP =0x0;

    EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;  // Enable the timer in count up/down mode

Thanks in advance

Lahiru

  • 0
    TI__Guru 52020 points

    Does your epwm outputs function as expected?

  • 0 in reply to Nima Eskandari
    Intellectual 270 points

    I am currently not using any ePWM outputs for my projects and I just want to generate ePWM interrupts. But ePWM outputs work fine when I execute another project of mine.

    Lahiru

  • 0 in reply to Nima Eskandari
    Intellectual 270 points

    Hi,

    I have tested the ePWM output of the same channel which I should generate interrupt. Output of the ePWM pin is worked intentionally.

    Thanks.

    Lahiru

  • 0 in reply to Nima Eskandari
    Intellectual 270 points

    Hi,

    Please help me to resolve the issue if possible.

    Thanks 

    Lahiru

  • 0 in reply to Lahiru Sandaruwan
    TI__Mastermind 42195 points

    Lahiru,

    the interrupt scheme can be complex. The TRM explains what you need to enable to allow the interrupts to propagate through the Peripheral Interrupt Expansion (PIE). A full explanation can be found in section 3.4.3 "Interrupt Entry Sequence" of the TRM.

    I think the easiest way to solve this would be to start from a PWM example in C2000ware that already configures the interrupts and then disable the GPIOs so that the PWM signal does not output. Try starting from this one: "C:\ti\c2000\C2000Ware_2_00_00_02\device_support\f2837xd\examples\cpu1\epwm_updown_aq\cpu01"

    After you get this running you should be able to make small incremental changes to what triggers the interrupts and get the behavior you want. For this look at ETSEL[INTSEL].

    Regards,
    Cody