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Hello,
I have a strange problem with C2000TM PiccoloTM F28004x Series LaunchPadTM Development Kit. I'm trying to get the SCI communication to work but I only receive bytes if I set a breakpoint some where where I read the bytes from SCI registers. I'm using FIFO and I tried with and without interrupt but with same result. As a SCI port I'm using the virtual COM-port provided from the toolkit (Linux - ttyACM0)
Without interrupt I have to set a breakpoint to somewhere where I wait for bytes to FIFO:
Polling the RXFSST
if (SciaRegs.SCIFFRX.bit.RXFFST > 0)
{
data_pu16 = SciaRegs.SCIRXBUF.all; (<- breakpoint here works)
.
.
.
.
}Or if I use interrupts, I have to set the breakpoint to interrupt handle routine. If I don't set breakpoint I do not get any data (it doesn't execute the path where the data handling is). I have also tried without debugger with the same result -> not receiving anything. I know that if I receive the bytes my program will answer correctly (works with breakpoint set).
SCI Init:
SciaRegs.SCICTL1.bit.SWRESET = 0;
SciaRegs.SCICTL1.bit.SWRESET = 1;
SciaRegs.SCICCR.all = 0u;
SciaRegs.SCICCR.bit.STOPBITS = 1;
SciaRegs.SCICCR.bit.PARITY = 0;
SciaRegs.SCICCR.bit.PARITYENA = 0;
SciaRegs.SCICCR.bit.SCICHAR = 7;
// Calculate and set baudrate
brr_u16 = (uint16_t)((LOW_SPEED_PERIPHERAL_CLOCK / (115200 * 8u)) - 1u);
SciaRegs.SCIHBAUD.all = (brr_u16 >> 8u);
SciaRegs.SCILBAUD.all = (brr_u16 & 0x00FFu);
SciaRegs.SCIPRI.bit.FREESOFT = 3u;
// Enable FIFO
SciaRegs.SCIFFTX.bit.TXFIFORESET = 1;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
SciaRegs.SCIFFTX.bit.SCIFFENA = 1;
SciaRegs.SCIFFTX.bit.SCIRST = 1;
SciaRegs.SCIFFTX.bit.TXFFIL = 0;
SciaRegs.SCIFFTX.bit.TXFFIENA = 1u;
SciaRegs.SCIFFRX.bit.RXFFIL = 1u;
SciaRegs.SCIFFRX.bit.RXFFIENA = 1u;
SciaRegs.SCICTL1.bit.TXENA = 1;
SciaRegs.SCICTL1.bit.RXENA = 1;
SciaRegs.SCICTL1.bit.SWRESET = 1;
SciaRegs.SCIFFTX.bit.TXFIFORESET = 1;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
// Sw reset module
SciaRegs.SCICTL1.bit.SWRESET = 0;
SciaRegs.SCICTL1.bit.SWRESET = 1;
// Enable transfer interrupt
EALLOW;
PieCtrlRegs.PIEIER9.all |= 0x0001; // Only if interrupt allowed
PieCtrlRegs.PIEIER9.all |= 0x0002;
IER |= M_INT9; // Enable CPU Interrupt group 9
EDIS;
// Configure RX pin
GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1);
GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC);
// Configure TX pin
GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1);
GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);Any ideas?
