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Original question:

TMS320F28027: Flash pipeline prefetch start address : even or odd?

TMS320F28027: TMS320F28377D

Sundaram Kaliyugavaratharajan
Prodigy 190 points

Part Number: TMS320F28027
Other Parts Discussed in Thread: TMS320F28377D

Hi,

We are using TMS320F28377D. I have 2 questions on this instruction prefetch and data cache options in the FMC.

1. Should the instruction buffer be considered as instruction cache?

2. What would be the performance degradation if the prefetch and data cache are disabled.

Thanks,

Sundaram

  • 0
    TI__Guru* 87155 points

    Sundaram,

    1. Yes, you can consider it as a instruction cache that gets filled in by the prefetch mechansim.

    2.  I can not give you a specific number as it depends on many factors like the address offset (from a 128-bit aligned address), instruction size, branches etc.      Assuming the code is sequential, if prefetch is disabled, you will incur Flash wait-states on each instruction fetch from Flash.  If prefetch is enabled, and say you made an access to address 0x80000, you will incur Flash wait-states on the first 128-bit fetch and it gets stored in the first 128-bit prefetch buffer.  While CPU is processing the first 32-bit or first 16-bit instruction, the rest of the bits in the fetched 128-bits are stored in the prefetch buffer and there is no additional wait-state involved to fetch from there.  Not just that, while the CPU is processing the instructions from the first 128-bits, prefetch mechanism will access the next 128-bits from Flash and fill it in the second level 128-bit prefetch buffer - meaning application did not loose any extra cycles due to this second fetch.  If code is sequential, then application did not incur wait-states for all the instructions that are in address range 0x80002 to 0x8000F (assuming the instruction at 0x80000 is a 32-bit instruction).  If prefetch is disabled, waitstates are incurred on each of these instructions - nearly 7x3 = 21 wait cycles (assuming 32-bit instructions).  

    Thanks and regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    Prodigy 190 points

    Thanks Vamsi for the detailed reply. I have one more question.

    What's the effect of data cache on wait-states and how does data-cache impact the CPU performance?

  • 0 in reply to Sundaram Kaliyugavaratharajan
    TI__Guru* 87155 points

    Sundaram,

    If the data is not available in the data cache, wait-states will be incurred to bring the data (a 128-bit aligned data segment) in to data cache (CPU gets it from here).  However, the entire 128-bit will get in to the data cache and not just the requested data.  Hence, if the next data request falls in to that 128-bit data in cache, there is no wait-state penalty.  Note that there is no further prefetch advantage to this (like the one that I explained for code space).

    Note that the 128-bit data that gets in to cache is always a 128-bit aligned data segment in the Flash memory.  For example, if CPU requests the data at address 0x80003 and if that is a miss, data cache gets filled with data from 0x80000 to 0x80007.  

    Thanks and regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    Prodigy 190 points

    Thanks Vamsi.

    1. Is this instruction buffer and data cache ECC/Parity protected? Ours is a safety critical system and hence we need to protect the memory that we use.

    2. Can we use the controller with 160 MHz system clock frequency in standard mode (code prefetch-mechanism and data cache are disabled)? 

    Thanks,

    Sundaram

  • 0 in reply to Sundaram Kaliyugavaratharajan
    TI__Guru* 87155 points

    Sundaram,

    1. I can understand. They are not protected. Flash content gets evaluated for ECC correctness before entering in to instruction buffer and data cache.  

    2. As I mentioned in the TRM section "3.12.8.1.1 Standard Read Mode", you can use it. But the performance will be poor since 3 wait-states (you need 3 waitstates at 160MHz) will be incurred on every Flash access since each access creates a unique flash bank access. 

    Thanks and regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    Prodigy 190 points

    Thanks Vamsi for your quick reply.