TMS320F28069M: Multi samaple PWM with F28069M; Immediate load mode of ePWM

Cody,

Thanks a lot for immediate reply. Your answer is very valuable as it has given me more insight about the operation of Immediate mode.

I have some more confusion related to this:

Can I use immediate load with HRPWM also?

And the refereed compare logic (TBCLK is at 25 and you update CMPA from 27 to 23) will also be applicable in HRPWM as now there will be CMPAHR to deal with in HRPWM mode?

Whether any extra precaution is required while operating in HRPWM with Immediate Load ?

With thanks & Regards,

Dipen

Dipen,

The HRPWM requires internal logic to update "lots of things" for the HR enhancements. This can only occur at TBCTR = PRD or TBCTR = ZERO because it is tied to the internal logic. This is why in Up-down-count mode you must use "load on CTR and ZRO" setting. If you updated a value after the HR portion had been loaded then you would see your non-HR portion of the PWM change, and then see the old HR portion be applied to that signal.

Regards,
Cody 

Cody,

Many thanks for your reply and helping me to understand better about the working of ePWM & HRPWM of TMS320F28069M especially with immediate load. 

I am in the process of lab-prototype development. Once ready (may be in Jan-2019), I am going to try the implementation of ePWM with immediate load for switching frequency of 25 kHz and sampling as well as PWM update at 250 kHz. I guess the accurate implementation of HRPWM with immediate load would be near to impossible.

I will surely share my experience about experimental results/findings related to this implementation.

With regards,

Dipen

Dipen,

I'm glad you recieved the information you needed.

Forgive me for not understanding, but why do you need to update your PWM 10 times per PWM period? What does updating so frequently get you over updating once per period?

Thanks,
Cody

Cody,

It is basically the phase lag created by the time delays due to the sample & Hold process as well as the PWM update that I would like to minimize. In fact ADC conversion time and computational time taken by the CPU in calculating the control law are also the part of time delays.

Neglecting the quantization effects due to finite resolution, Digital PWM generation can be modeled as ideal sampler followed by zero order hold (ZOH) whose transfer function can be approximated in s-domain as exp(-s*Tsamp/2) which leads to time delay of Tsamp/2 in the feedback loop.

Considering the symmetric PWM generation scheme as given on page-3 of http://www.ti.com/lit/an/spraab3/spraab3.pdf, total value of ADC, computational and PWM update delay can be Tsamp/2.

Now consider my application of DC-DC converter having switching frequency (fsw) of 25 kHz in which I am planning to obtain feedback crossover frequency or bandwidth of 2.5 kHz (fsw/10). If I go for single sample PWM scheme having pwm update once per period i.e Tsamp = Tsw = 40us, I will be having total time lag of 20us (due to ZOH) + 20us (due to delay) = 40us which leads to phase lag of 36 degree at my crossover frequency of 2.5 kHz and my phase margin is degraded by same amount.

Now if I go for multi sample PWM scheme having sampling frequency 10 times the switching frequency i.e. fsamp = 10*fsw, I will be having total time delay of 2us + 2us = 4us resulting in phase lag of 3.6 degree at 2.5 kHz.

Thus, by updating the PWM 10 times in the one PWM period, I can have phase boost of 36 - 3.6 = 32.4 degree at my cross over frequency. This is quite substantial gain and it not only makes my controller design more robust but also enables me to achieve higher bandwidth for same phase margin approaching the maximum bandwidth obtainable with analog solution. This is why I am exploring the ways to implement the so called multi sample PWM in TMS320F28069M

Many thanks for your interest in my application and you are most welcome for the same !

With regards,

Dipen