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TMS320F28375S: ADC conversion results show periodic variation

Koichiro Tashiro
Mastermind 22945 points

Part Number: TMS320F28375S

Hi,

My customer using TMS320F28375S reported strange behavior in the device ADC.

In customer’s system, ADC is used to monitor fixed voltages on the board.
Here is a snapshot of schematics around ADC inputs.


According to customer, all inputs have 20mV~30mV variation and ADC is configured 12-bit resolution,
so expected ADC conversion variation is ~40 counts.
But actual results shows ~600 counts.

Example results are attached.
ADC_Error.xlsx
“raw data” sheet is raw data.
Column C to H correspond to inputs PN15, P15, PN5, P5, P33, P18 in above schematics, respectively.
Column A is sample# and each sample is 2msec separated.
And PN5 shows spike at sample#72 which is 3895 counts.

“zoom-up” shows zoom-up version of the same data. In this figure, each data seem random.
“time shift” is the same data with each input is shifted a several sample#. In this case, all data show 20msec cycle.

Customer checked ADC reference voltage and it is no problem.
ADC configuration is below.

Fullscreen ADC_configuration.txt Download 
/* ================================================================ */
/* ADC�����ݒ� */
void SetupADC(void)
{
//Select the channels to convert and end of conversion flag
    EALLOW;
    //ADC_A
    /*CPU TIMER2 SOC0~3*/
    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 2;      //SOC0 pin A2 PN15
    AdcaRegs.ADCSOC1CTL.bit.CHSEL = 3;      //SOC1 pin A3 P15
    AdcaRegs.ADCSOC2CTL.bit.CHSEL = 4;      //SOC2 pin A4 PN5
    AdcaRegs.ADCSOC3CTL.bit.CHSEL = 5;      //SOC3 pin A5 P5
//    AdcaRegs.ADCSOC0CTL.bit.ACQPS = 20;     //sample window is 20 + 1 SYSCLK cycles �F 5ns �~ 21 = 105ns
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = 399;     //sample window is 399 + 1 SYSCLK cycles �F 5ns �~ 400 = 2��s  // (2��s/sysclk�y=5ns =1/2MHz�z) - 1 =399
    AdcaRegs.ADCSOC1CTL.bit.ACQPS = 399;
    AdcaRegs.ADCSOC2CTL.bit.ACQPS = 399;
    AdcaRegs.ADCSOC3CTL.bit.ACQPS = 399;
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 3;    //CPU1_Timer2(2ms)
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 3;
    AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 3;
    AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 3;


    //ADC_B
    /*CPU TIMER2 SOC0~1*/
    AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2;      //SOC0 pin B2 P33
    AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3;      //SOC1 pin B3 P18
    AdcbRegs.ADCSOC0CTL.bit.ACQPS = 399;
    AdcbRegs.ADCSOC1CTL.bit.ACQPS = 399;
    AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 3;    //CPU1_Timer2(2ms)
    AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 3;


    //ADC_C
    /*CPU TIMER2 SOC0~2*/
    AdccRegs.ADCSOC0CTL.bit.CHSEL = 2;      //SOC0 pin C2
    AdccRegs.ADCSOC1CTL.bit.CHSEL = 3;      //SOC1 pin C3
    AdccRegs.ADCSOC2CTL.bit.CHSEL = 4;      //SOC2 pin C4
    AdccRegs.ADCSOC0CTL.bit.ACQPS = 399;
    AdccRegs.ADCSOC1CTL.bit.ACQPS = 399;
    AdccRegs.ADCSOC2CTL.bit.ACQPS = 399;
    AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 3;    //CPU1_Timer2(2ms)
    AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 3;
    AdccRegs.ADCSOC2CTL.bit.TRIGSEL = 3;



    //ADC-D
    /*CPU TIMER2 SOC0~4*/
    AdcdRegs.ADCSOC0CTL.bit.CHSEL = 0;      //SOC0 pin D0
    AdcdRegs.ADCSOC1CTL.bit.CHSEL = 1;      //SOC1 pin D1
    AdcdRegs.ADCSOC2CTL.bit.CHSEL = 2;      //SOC2 pin D2
    AdcdRegs.ADCSOC3CTL.bit.CHSEL = 3;      //SOC3 pin D3
    AdcdRegs.ADCSOC4CTL.bit.CHSEL = 4;      //SOC4 pin D4
    AdcdRegs.ADCSOC0CTL.bit.ACQPS = 399;
    AdcdRegs.ADCSOC1CTL.bit.ACQPS = 399;
    AdcdRegs.ADCSOC2CTL.bit.ACQPS = 399;
    AdcdRegs.ADCSOC3CTL.bit.ACQPS = 399;
    AdcdRegs.ADCSOC4CTL.bit.ACQPS = 399;
    AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 3;    //CPU1_Timer2(2ms)
    AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = 3;
    AdcdRegs.ADCSOC2CTL.bit.TRIGSEL = 3;
    AdcdRegs.ADCSOC3CTL.bit.TRIGSEL = 3;
    AdcdRegs.ADCSOC4CTL.bit.TRIGSEL = 3;
    AdcdRegs.ADCINTSEL3N4.bit.INT4SEL = 4; //end of SOC4 will set INT4 flag
    AdcdRegs.ADCINTSEL3N4.bit.INT4E = 1;   //enable INT4 flag
    AdcdRegs.ADCINTFLGCLR.bit.ADCINT4 = 1; //make sure INT4 flag is cleared

    EDIS;
}

Could you give us any advices to check?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru 60865 points

    Hi Tashiro-san,

    What method did they use to check the reference?  DC check via DMM, or time-series check via oscilloscope?  It may be worth checking the reference for oscillations via a check with an oscilloscope.  Also, what is the IC driving the references?  Is it stable when driving ~4uF of capacitance directly? 

    The 20mS period corresponds to a 50Hz signal.  Is the system generating/controlling the 50Hz signal?  If so, is the power stage isolated from the MCU?  It may be worth using an oscilloscope to check the grounds of the ADC signal capacitors, VREFLO, the grounds and supplies for the clamping diodes, etc. to see if the 50Hz signal can be observed coupling into the signal or reference path.

    Are the 0.1uF capacitors placed physically close to the ADC pins?  0.1uF should be enough to charge-share with the internal ADC S+H capacitor, so a S+H time near minimum should actually be OK (looks like the configuration file shows S+H = 400 x 5ns = 2uS?). 

    When charge-sharing, the trade-off is between sample rate (on a given channel) vs external impedance.  If the ADC samples too fast, charge will bleed-off from the external capacitors from each subsequent sample faster than it can be recharged to the forced voltage via the voltage divider.  You might try reducing the sample rate to see if the performance changes (but you should also be able to see this much variation directly with a scope on the input pin, so maybe this is unlikely an issue).

    In addition to the settings you supplied, you should also probably verify the SYSCLK (should be <= 200MHz), ADCCLK (should be <= 50MHz), and ADC signal mode (should be single-ended).