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Tool/software: Code Composer Studio
Hi,
My EPWM CLOCK is at 100 MHz and TB clock at 1.5625 MHz (i.e. CLKDIV and HSPCLKDIV both divided by TB_DIV_4 ( 100 M / 8*8)),
from the TRM given for F28379D, while calculating FPWM (1/2*TBPRD*Time of TB Clock(1/1.5625M)), when both CLKDIV and HSPCLKDIV are set at same value, i am getting my frequency doubled than it should be. Why so ?
For other combination of CLKDIV and HSPCLKDIV it is coming correct.
By default it is given in TRM that CLK_DIV is set at TB_DIV_1 (i.e. 000/1) and HSPCLKDIV at TB_DIV_1 (i.e. 001 / 2).
Please suggest asap.
Can you share a screenshot of your “predefined symbols” in your project properties compiler setting?
so till now if TB_DIV_1 and TB_DIV2 is not defined then what values program was taking, when I have assigned these lines to bit ? How do i define them , like in decimal or binary ? I mean the assigned values should be pre-scaling values or bit values ?
Those are defined and available in your epwm header files. That is not what we changed above by adding the macro. The macro actually corrected your SYSCLK frequency. Please review http://www.ti.com/lit/ug/spruhm8i/spruhm8i.pdf for more information on the EPWM registers.