TMS320F28035: TMS320F28035 memory architecture

Karl Stewart1 said:

This might seem like a very simple question, but looking at the technical reference manual (SPRUI10) it's not conclusively clear. Maybe is exists in the documentation for a near identical device, but I wouldn't know where to start looking.

I want to know what is the RAM architecture of the TMS320F28035 device, and specifically which blocks are shared between the CLA and CPU, and what access restrictions/arbitration applies.

Hi Karl,

The TRM (technical reference manual) has information on peripherals without much about how they are glued together on the device.  The datasheet shows how the peripherals are connected together (clocking, memory blocks, etc). 

For the info you are looking for, take a look at the memory map section of the TMS320F28035 datasheet (figure 6-1).  The message RAMs are at 0x1400 and 0x1500.  Blocks that the CLA can use are indicated (i.e. "CLA Data RAM 0" or "CLA Prog RAM").

I hope this helps.  If it resolves your question please let me know by pressing the "verified answer" button.  If not, please provide additional details.

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Regards

Lori

Thanks for the info Lori.

Okay, so I now know the location of the CLA/CPU message RAM (I was expecting it see it in the block diagram). But surely there is an arbitration scheme to manage concurrent accesses (for example when the CLA wants to read and the CPU wants to write). What are the rules in this case?

L1, L2 and L3 are described as DPSARAM (dual port SARAM), whereas L0 is merely SARAM, so I assume then that it's single port? But who has access to it, the CPU or the CLA?

Karl

Karl Stewart1 said:

But surely there is an arbitration scheme to manage concurrent accesses (for example when the CLA wants to read and the CPU wants to write). What are the rules in this case?

Karl,

Please refer to the TRM section 10.3 which describes the CPU and CLA arbitration when accessing message RAM, program memory and data RAM.

Karl Stewart1 said:

L1, L2 and L3 are described as DPSARAM (dual port SARAM), whereas L0 is merely SARAM, so I assume then that it's single port? But who has access to it, the CPU or the CLA?

All blocks on the device are accessible by the main C28x CPU. Only blocks that have the CLA mentioned are accessible by the CLA.  Yes, SARAM is a single port single access RAM.  DPSARAM is dual port (one for C28x and one for CLA) single access RAM. 

Regards

Lori