TMS320F28069: PIEACK seems cleared automatically in some cases.

Hitoshi Sugawara

Mastermind 19700 points

Part Number: TMS320F28069

Hi Champs,

According to the TRM, PIEACK msut be cleared by SW.
However, PIEACK seems automatically cleared when 0 is written onto PIEIERx register.
Is it the correct behavior as TI's specification.

This is the example code for ADCINt1 ISR as follows:

interrupt void IntrHndr_adcint1( void )

{

volatile SDT_UINT16 u16_PieIer = (SDT_UINT16)PieCtrlRegs.PIEIER1.all;

IER |= M_INT1;

IER &= MINT1;

PieCtrlRegs.PIEIER1.all &= (SDT_UINT16)MG11; /* Note: MG11=0x0000. PIEACK is cleared after that. */

SDC_ASM_NOP;

EINT;

intrAdc_ConvEnd( );

PieCtrlRegs.PIEACK.all = 0x0001;

DINT;

PieCtrlRegs.PIEIER1.all = u16_PieIer;

}

Moreover, the PIEACK would be also cleared when the group interruptions are all disabled by PIEIERx register.

Could you please check if the condition are correct expectedly or not.
Thank you for your kind support.
Best regards,
Hitoshi

over 5 years ago

0 Ken Schachter over 5 years ago

TI__Genius 17315 points

Hitoshi,

The core IFR is automatically cleared when entering the ISR - for more detailed information please see section 3.4 on page 58 in the TMS320C28x CPU and Instruction Set Reference Guide (spru430). Also, when entering the ISR the INTM is set to prevent nested interrupts and it is automatically cleared when exiting the ISR.

The PIEIFR on the other hand is manually cleared in software by writing to the PIEACKx register. (That is, the PIEACKx instruction is used to clear the PIEIFR in the ISR). The typical user working with interrupts does the following (using ADC as an example) in their code:

1) Enable global interrupts

asm(" CLRC INTM"); // Enable global interrupts - or done with EINT in main() function

2) Enable the peripheral and core interrupt

PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable ADCINT1 in PIE group 1
IER |= 0x0001; // Enable INT1 in IER to enable PIE group

3) In ISR acknowledge the interrupt and clear the PIEIFR

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Must acknowledge the PIE group

For more information please the module 4 and lab 5 in the F28069 workshop at:

https://training.ti.com/c2000-f2806x-microcontroller-workshop?context=1137791-1137782

Note that in the workshop we acknowledge the interrupt in the beginning of the ISR rather than the end. This allows us to catch another pending interrupt while running the ISR.

I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

- Ken

0 Hitoshi Sugawara over 5 years ago in reply to Ken Schachter

TI__Mastermind 19700 points

Hi Ken,

Thank you for the procedure.
May I clarify about my specific questions as follows?

1) PIEACK seems automatically cleared when 0 is written onto PIEIERx register.
Is it correct?

2) the PIEACK would be also cleared when the group interruptions are all disabled by PIEIERx register.
Is this correct too?

Thank you very much for making the simple answers.
Best regards,
Hitoshi

0 Ken Schachter over 5 years ago in reply to Hitoshi Sugawara

TI__Genius 17315 points

Hitoshi,

In the TRM we can not find any references to the PIEACKx being cleared when writing to the PIEIERx register. The interrupt process with respect to the PIEIFR, PIEIER, and PIEACK is as follows:

1. PIEIFRx will be set irrespective of the state of PIEIERx. PIEIFRx is automatically cleared by hardware after the interrupt is take by the CPU. Software clearing of PIEIFRx is frowned upon since it can lead to race conditions.

2. PIEACKx is manual clear only. We are not aware of any instance where it will be automatically cleared. This is why the in the interrupt flow, we tell customers not to forget to manually clear PIEACKx or else no further interrupts will be taken for that group.

3. Clearing PIEIERx disables that interrupt line. This is also manual to give customers the option to enable or disable that interrupt line.

In the F2806x TRM please see section 1.7.1.1 on page 167 and figure 1-94 on page 168 for more details.

I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

- Ken

0 Hitoshi Sugawara over 5 years ago in reply to Ken Schachter

TI__Mastermind 19700 points

Hi Ken,

Thank you so much for your kind explanation.
I would like to share the information off line.

Please close the thread.
Thank you again.
Best regards,
Hitoshi

0 Ken Schachter over 5 years ago in reply to Hitoshi Sugawara

TI__Genius 17315 points

Hitoshi,

I ran a further test using the workshop code and observed these results. If "inside the ISR" you have the following:

//PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Must acknowledge the PIE group <<LINE COMMENTED OUT>>

PieCtrlRegs.PIEIER1.bit.INTx1 = 0x0; // This clears PIEIER1 bit only and not the PIEACK

PieCtrlRegs.PIEIER1.all = 0x0000; // This clears PIEACK

However, you would need to set the PIEIERx again to receive subsequent interrupts. As stated in my earlier post, the PIEIER is not typically managed in the ISR, but within the initialization code.

- Ken

0 Ken Schachter over 5 years ago in reply to Ken Schachter

TI__Genius 17315 points

Hitoshi,

Minor update to my previous post - you can modify the PIEIERx in an ISR, but it must be done only for that group (i.e. PIEIERx in a group x interrupt) and must be done while PIEACK is holding off interrupts. This is what we do in our nested interrupt scheme, which looks like the code snip you started with.

- Ken

0 Hitoshi Sugawara over 5 years ago in reply to Ken Schachter

TI__Mastermind 19700 points

Hi Ken,

Thank you so much for your kind experiment for PIEACK condition.
It seems the symptom is duplicated by your test too.
Will bring it to the customer and confirm with them.

Thank you again for your skillful investigation.
Best regards,
Hitoshi

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TMS320F28069: PIEACK seems cleared automatically in some cases.