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Original question:

CCS/TMS320F28377D: Extended Wait Mode and the EM1WAIT Pin

CCS/TMS320F28377S: Unable to reduce MAX_EXT_WAIT

Saravanakumar Kandhallu Dwarakan
Prodigy 80 points

Part Number: TMS320F28377S

Tool/software: Code Composer Studio

Hi,

I have configured EMIF1 to access Dual Port RAM Asyn device. I am facing a  problem with WP0 and MAX_EXT_WAIT.  

Test 1:  Configuration:

reg_EMIF1->ASYNC_WCCR.bit.WP0 = 1u;

reg_EMIF1->ASYNC_WCCR.bit.MAX_EXT_WAIT = 0x40u;

Problem: Even though i have reduced max ext wait time to 0x40, it always wait for 0x80 time period. i don't understand why? 

Test 2: Configuration:

reg_EMIF1->ASYNC_WCCR.bit.WP0 = 0u;

reg_EMIF1->ASYNC_WCCR.bit.MAX_EXT_WAIT = 0x40u;

Problem: Even though i have set WP0 set to 0u. When WP0 is set to 1, It starts to wait for 0x80 time period. i don't understand why? 

For the above tests,

/* EMIF1 ASYNC CS2 Configuration*/

#define ASIZE_16 0x01u /* 16Bit Memory Interface */
#define POLARITY_HIGH 0x01u
#define EMIF_MAJOR_REVISION 0x02u
#define EMIF_MINOR_REVISION 0x05u
#define LITTLE_ENDIAN 0x00u
#define EMIF1_CLK_ENABLE 0x01u

#define TURN_AROUND_TIME 0x03u /* Turn Around time of 1 Emif Clock */

#define RD_SETUP_TIME 0x04u /* Read Setup time of 1 Emif Clock */
#define WR_SETUP_TIME 0x04u /* Write Hold time of 1 Emif Clock */
#define RD_STROBE_TIME 0x4u /* Read Strobe time of 1 Emif Clock */
#define WR_STROBE_TIME 0x4u /* Write Setup time of 1 Emif Clock */
#define RD_HOLD_TIME 0x07u /* Read Hold time of 1 Emif Clock */
#define WR_HOLD_TIME 0x07u /* Write Hold time of 1 Emif Clock */

#define ASYNC_EW_ENABLE 0x01u
#define ASYNC_SS_DISABLE 0x00u


reg_EMIF1->ASYNC_CS2_CR.bit.ASIZE = ASIZE_16;
reg_EMIF1->ASYNC_CS2_CR.bit.TA = TURN_AROUND_TIME;
reg_EMIF1->ASYNC_CS2_CR.bit.R_HOLD = RD_HOLD_TIME;
reg_EMIF1->ASYNC_CS2_CR.bit.R_STROBE = RD_STROBE_TIME;
reg_EMIF1->ASYNC_CS2_CR.bit.R_SETUP = RD_SETUP_TIME;
reg_EMIF1->ASYNC_CS2_CR.bit.W_HOLD = WR_HOLD_TIME;
reg_EMIF1->ASYNC_CS2_CR.bit.W_STROBE = WR_STROBE_TIME;
reg_EMIF1->ASYNC_CS2_CR.bit.W_SETUP = WR_SETUP_TIME;
reg_EMIF1->ASYNC_CS2_CR.bit.SS = ASYNC_SS_DISABLE;
reg_EMIF1->ASYNC_CS2_CR.bit.EW = ASYNC_EW_ENABLE;

Thanks

Saravanan

  • 0
    TI__Guru** 117371 points

    Hi Saravanan,

    I am looking into this. Will get back to you before Monday.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 117371 points

    Hi Saravanan,

    From what you have explained, I am suspecting that the EMIF configuration is not happening properly in ASYNC_WCCR register for the WAIT feature. Have you looked into the EMIF configuration register value in CCS register view after code execution to make sure expected configuration is written into register?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 80 points

    Hello Vivek,

    Yes, I could able to see that the ASYNC_WCCR registers are populated correctly based on test configuration. I went into debug mode and viewed those registers too. Example,In Debug mode for Test Configuration 1, ASYNC_WCCR.bit.WP0 = 1u and ASYNC_WCCR.bit.MAX_EXT_WAIT = 0x40 registers were set properly for Emif1Regs.

    Based on our design, we use the below configuration 

    Test 1:  Configuration:

    reg_EMIF1->ASYNC_WCCR.bit.WP0 = 1u;

    reg_EMIF1->ASYNC_WCCR.bit.MAX_EXT_WAIT = 0x40u;

    EM1WAIT is always set to high. When an read request is issued to DPRAM, it acknowledges by transitioning EM1WAIT from high to low, so that DSP can read from it. When read request fails, it waits for MAX_EXT_WAIT of 0x80 instead of 0x40 time period.

    Thanks

    Saravanan

  • 0 in reply to Saravanakumar Kandhallu Dwarakan
    TI__Guru** 117371 points

    Hi Saravanan,

    If you have scope snapshot for chip select, read strobe and WAIT singal, can you share.

    Regards,

    Vivek Singh