• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 81 subscribers
  • Views 619 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049: SPI behavior when SPISTE signal shakes due to noise, etc.

Tomotaroh Kohro
Genius 15745 points
Part Number: TMS320F280049

Support team.

 

I would like to know about SPI behavior against SPISTE.

I understood normal behavior from the below sentence in TRM.

 

=======================================

The SPISTE pin operates as the slave-select pin. An active-low signal on the SPISTE pin allows the slave SPI to transfer data to the serial data line; an inactive- high signal causes the slave SPI serial shift register to stop and its serial output pin to be put into the high-impedance state. This allows many slave devices to be tied together on the network, although only one slave device is selected at a time.

=======================================

(1) I believe that the receiving of SPI (Slave) cannot receive during SPISTE signal is high as hardware behavior from the above sentence.

 

I want to know about the case where SPISTE signal changes from Active-Low to High and returns to Active-Low in a range smaller than 1CLK.

(2) In this case, does the receiving of SPI continue to work continuously ?

(3) I want to know how many clocks SPISTE signal is HIGH for stopping the receiving SPI(Slave).

 

Best Regards

KORO

 

  • 0
    TI__Guru 55700 points

    Tomotaroh,

    Can you please clarify the following questions about your setup?

    1) You are trying to use F280049.SPI is slave mode. correct?

    2) You have mentioned that SPISTE signal changes state from active low to active high for  1 CLK? What exactly is the duration of the clock? Also, are you talking about SYSCLK / SPICLK?

    3) Do you have any waveforms which you can share?

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Genius 15745 points

    Hello Manoj-san

    Thanks a lot for your reply.

    1) You are trying to use F280049.SPI is slave mode. correct?

    Yes, this is slave mode communication.

    2) You have mentioned that SPISTE signal changes state from active low to active high for  1 CLK? What exactly is the duration of the clock? Also, are you talking about SYSCLK / SPICLK?

    Yes, I mentione that SPISTE signal is swinging within 1CLK.
    I want to know whether SPI receiving process can be continued or not if SPISTE signal is swinging within 1CLK by noise and so on.

    3) Do you have any waveforms which you can share?

    No. now our customer is desging thier system.
    Customers are considering the risks of the system.

    Best Regards

    KORO

  • 0 in reply to Tomotaroh Kohro
    TI__Guru 55700 points

    Koro,

    Any noisy glitch (high pulse) on SPISTE would make SPI signals go into high-impedance state resulting in loss of communication. SPISTE signal goes through synchronizer which can sample any input glitch as valid transaction.Once SPISTE pins goes and meet the setup time of STE communication would resume.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Genius 15745 points

    Hello Manoj-san

    Thanks a lot.

    Your quick reply is very helpful for us.

    I will discuss about this point with customer. Then I want to close this ticket.

    Br

    KORO

  • 0 in reply to Tomotaroh Kohro
    TI__Guru 55700 points

    Koro,

    Can you please close this ticket?

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Genius 15745 points

    Hello Janoj-san

    Thanks a lot for your support.

    And I am sorry for late reply.

    I confirmed it there is an additional question related to on this.

    There is no additional question.

    This ticket can be closed.

    Br

    KORO