TMS320F28388D: Interferences on access to MSGRAM

Clément Letonnelier

Part Number: TMS320F28388D

Hi,

Related to my previous question, I have a question related to the MSGRAM between CPU.

These RAM are each dedicated to a specific direction, eg. from CPU1 to CLA1 or CLA1 to CPU1.

However, I am trying to ensure that there is no interference in case both sides of those memories access it at the same time, obviously one side in read and the other in write.

Are these memories double port memories ? Or is there any arbitration or priority not stated in the datasheet ?

Thanks,

Clément

over 5 years ago

0 Vivek Singh over 5 years ago

TI__Guru** 115431 points

Hi Clement,

Are these memories double port memories ? Or is there any arbitration or priority not stated in the datasheet ?

MSGRAMs are single port memory and have same arbitration scheme as GSxRAM.

Regards,

Vivek Singh

0 Clément Letonnelier over 5 years ago in reply to Vivek Singh

Expert 2816 points

Hi,

Really ?

This is not stated in the documentation. You meant the fixed priority schema and round robin ?

In that case, I don't see the advantage of those memories compared to the global shared RAMs.

Clément

0 Vivek Singh over 5 years ago in reply to Clément Letonnelier

TI__Guru** 115431 points

Hi Clement,

Arbitration scheme is same for all the shared RAMs and below is what we have in TRM. Yes user can use the Global shared RAMs as well. MSG RAMs are small block of RAMs and provided for specific usecase.

But look like it was still confusing so I'll provide this feedback to team and see if they can add some note in document for this.

Regards,

Vivek Singh

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28388D: Interferences on access to MSGRAM