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TMS320F28379D: Illegal interrupt after reset

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Hello,

I have written a small test program which has three eCAP interrupts. After downloading the program with the debugger everything works as expected. The program runs in the RAM.

 

Then I stop the program with the debugger and make a reset. To ensure to start the program out of the RAM the EMU_BOOTMODE is switched to SARAM.

 

When I start the program again it possible to run until the line with the “EINT” instruction is reached. After enabling the interrupts the DSP runs to the ILLEGAL_ISR and the debugger stops (due to the estop0 instruction in the handler).

 

What is the reason for this illegal interrupt?

 

 

Thank you very much

Ralf

  • Hi Ralf,

    Then I stop the program with the debugger and make a reset. To ensure to start the program out of the RAM the EMU_BOOTMODE is switched to SARAM.

    What kind of "reset" you are issuing ? Have you checked the code in RAM (CCS dis-assembly window) before running after reset ? You can put a breakpoint at main() and then step through the code and observe the code in disassembly window to see if you see any ITRAP instructions there.

    Regards,

    Vivek Singh

  • Dear Vivek,

    I have made some screenshots to clear the situation. Please look at the attachment.

    Best regards

    Ralf

    The reset is issued from the debugge1.pdf

  • Thank you. So you step through the code, it works fine. Can you insert some delay between EINT and ERTM instruction and see if that helps.

    Regards,

    Vivek Singh

  • Dear Vivek,

    I have inserted a delay of one millisecond. Unfortunately the result is the same (see screenshot)

    Best regards

    Ralf

  • Dear Vivek,

    I have one additional information.

    The only way to restart the the program is to cancel the debug session. If you start then the debugger again it workes (until you make a reset).

    Best regards

    Ralf

  • Do you power cycle the board or just disconnect the CCS and connect again? Also when CPU halts at EINT, can you check the NMIFLG register value in CCS register view.

    Regards,

    Vivek Singh

  • Dear Vivek,

    the power on cycle does not resolve this problem. But I have found out something different.

     The interrupt service routine of ecap1_isr starts at address 0x122.

     

     

    As long as no reset is issued everything works fine. The next picture shows the disassembly when the DSP is reset and the program counter points to the reset vector. At this point the mnemonic at address 0x122 is ok (ASP).

     

     

    Now the DSP is started and runs to main().

     

     

    Here you can see, that the boot routine has overwritten the mnemonic at address 0x122. The ASP instruction is replaced with an ITRAP0! This is the reason for the illegal interrupt.

     

    Why is the address 0x122 overwritten by the boot routine?

     

    Thank you very much

    Ralf

  • Hi Ralf,

    This is good info. Earlier you mentioned, if you step through the code then you don't see this issue ?

    Before we look into BOOTCODE, can you try one more thing. After loading the code Ist time (check that value at 0x122 is correct), do not run the code. Instead issue a reset put a breakpoint on "code_start" and then run it so that CPU halts at "code_start" and then check the value at 0x122. If the value is correct then value is not over written by BOOTROM but may be by your application.

    Regards,

    Vivek Singh

  • Dear Vivek,

    I have checked the single step operation again. You can step through the code until the first subroutine is called. After that the controller jumps to the illegal interrupt.

     

     

    I have downloaded the code and set a breakpoint at codestart. In this case the breakpoint is not reached. I guess the reason for this is that after downloading the code the controller runs automatically to main().

     

    In order to make a check I have done the following steps.

    Download the code and check the address 0x122.

    At this time address 0x122 is ok.

    After that the EMU_BOOT_MODE is switched to SARAM and a reset is issued.

    The program counter is set to 0x3ff16a. The code at address 0x122 at this time is still ok. 

    Now I have set a breakpoint at codestart and run the code.

    The program counter stand at address 0x000000. At this time the code at address 0x122 is overwritten!

    If you want I can send you the project with the source code. It is very small and runs on the launchpad of the 28379D.

    Thank you very much

    Ralf

  • Dear Vivek,

    I think I have additional informations. I have made a single step through the bootloader.

    At adress 0x3ff1ff is a loop which writes zeros into the memory. The screenshot shows the time when the SP contains 0x42. At this time accumulator holds 0xe0, the number of the loop counts. You can see at address 0x122 in the memory windows the correct opcode.

    I have set a breakpoint at 0x3ff203 (after the loop).

    After the end of the loop the opcode at address 0x122 is overwritten with zero (see memory window).

    Is this a problem in the bootroutine?

    Best regards

    Ralf

  • Hi Ralf,

    Thanks. I used CCS "Hardware Watchpoint" feature to halt the CPU on write to 0x122 address and I can see the same thing. That section of the code in BOOTROM is doing stack initialization and 0x122 is the last location hence it is getting initialize.

    I looked into the device TRM (BOOTROM section) and it is mentioned there that RAM from 0x02 to 0x122 is reserved for BOOTROM usage. Please see the below snapshot from device TRM.

    So you should not use that location for your code. I looked at the sample linker cmd file provided in C2000Ware and that has an issue. In that definition of M0 is from 0x122 which is not correct. It should be 0x123. Please correct this in your linker cmd file and that should help.

     RAMM0            : origin = 0x000122, length = 0x0002DE

    We'll correct the sample linker cmd file in next release.

    Thank you for debugging this and our apology that this has caused the inconvenience to you.

    Regards,

    Vivek Singh