CCS/TMS320F280049C: RealTime debug XDS110 bounces

Seemingly ADC offset calculation and Clarke_run transform via motor SDK is not using the correct sample positions. That offset calculation and mainISR() pull down the DC supply (CH2) as the inverse bus voltage may actually be using +1.65v mid supply of INA240 values. Who would be the wiser if the SDK was never tested with external current sensor/s versus using the internal PGA amplifiers? Should the PGA outputs threshold be mid supply by the DAC +1.65v configuration of motor SDK, was that confirmed or assumed?

No matter the ADC analog input configured for INA240 (40mV/A), disabling 3x PGA's the XDC110 bounced every time +3v3 (1A) LDO pulled down -6.2Amps (CH2 -240/-280mV). Seemingly INA240 outputs should not be pulled below +1.65v threshold but for single transient 50% dutycycle (25µs). CH2 reveals it was dragged below +1.65v for over 200µs. The 3 ADC inputs A,B,C replaced x49c PGA's disabled current monitors.

Note how CH1 never recovers to even mid supply as CH2 drags +3v3 LDO below +1.65v threshold (INA240). Each with 4K7 series into analog channel,  filters PGA_2OF, PGA_4OF, PGA6_OF C32,C33,C34 respectively are low pass input filters of disabled PGA amps passed into ADC (TRM: Fig.12-4). Again even analog C3, C5, A3 and lastly B0 were used for INA240 inputs rendering the very same results shown below. Of course the respective ADC base address and analog input pin source was selected for each SOC that had belonged to PGA-A,B,C. Also tested the GxADCAB, Gx_ADCCC inputs had the same bad results. 

The DRV8320RS kit current sense PGA threshold set input bias via x49c DAC configured +1.65v. Perhaps the resistor network into the 3x PGA's does not set PGA outputs at mid supply +1.65v into the ADC as expected it should.  

Biased inputs 3x PGA amplifiers +IN via x49c DAC, should set ADC threshold (+1.68v). BoostXL-DRV8320RS resistor network sets PGA +IN (140mV) x12 gain, should set amplifiers output (+1.68v). Seemingly the PGA gain (x12) was not setting outputs 1.68v for ADC divide 2048 counts. Otherwise the INA240 bidirectional current output set mid supply (+1.65v) would not rapidly pull down VDD +3v3 rail or reset MCU via xRSn U4.

 Can anyone please confirm how motor SDK is not compatible with INA240 current sensor versus x49c PGA? I never did like splitting the ADC mid supply believing phase current has slope and magnitude. The INA240 forum gurus challenge such notion standing by mid supply ADC split being the holy grail. Yet the linear current approach <1.65v reference seems to produce better SAR ADC digital results. 

GI,

Answers to initial questions below.

(1) Answered in latest reply in previous thread: https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/885802/3280133#3280133

(2) Are you using an isolated power supply for the XDS110 / DuT side of the board? Thinking the isolation may be getting compromised somehow.

(3) Reset sources are documented in section 3.4 Resets of the device TRM. Should look into power / isolation issues of (1) and (2) first

Best,

Kevin

Kevin Allen18 said:

(2) Are you using an isolated power supply for the XDS110 / DuT side of the board? Thinking the isolation may be getting compromised somehow.

Yes but it seems the XDS110 should be powered via U101 (+3v3) when JP2 is removed as to isolate it from the target (DUT) +3v3 LDO. I'm not sure what is gained by removing JP2 but only to isolate U101 from nothing!

The idea is to isolate XDS110 USB connection completely from the target DUT, not the USB port +VBUS power source from XDS110 as it now does. The reason for having 3v3 isolation for target DUT seems obvious how CCS debug gets all snooty.  

Kevin Allen18 said:

(3) Reset sources are documented in section 3.4 Resets of the device TRM.

Was referring to CCS register view reset cause bits being set. So is there any expected bug in CCS9.1 or XDS110 that causes a rapid reset?