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LAUNCHXL-F28069M: ADC: Initial Conversion, Timing of ADC first sample

Dipen Vachhani
Prodigy 90 points
Part Number: LAUNCHXL-F28069M

Hi

My question is related with the ADC Timings - total conversion time for first conversion.

Silicon Errata: SPRZ342N mentions the non-reliability of first ADC conversion result. Whether the ADC clock cycle consumed by ADC for the first conversion is also unreliable?

I mean my ACQPS value is 18 and practically I am getting total conversion time for the first sample is about 1.25 us (~56 ADC clock cycles). As per theory, I should be getting about (2+19+15 = ~36 cycles)

If I convert two ADC channels in sequential mode (with overlap) with ACQPS = 18 for both channels, I am getting total conversion time of 1.8 us (~82 clock cycles). That is 82-56 = 26 cycles more than the first conversion which I think is in line with ADC timing  diagram given in section 8.1.12 of SPRUH18G.

I suspect that the ADC is taking more cycles to finish the first sample conversion, am I right?

I am initaiting ADC SOCs by ePWM TBCTR = 0.

With Thanks & Regards,

Dipen

  • 0
    TI__Guru 60865 points

    Hi Dipen,

    No, the first conversion doesn't have timings any different than other conversion or than the technical documentation indicates.

    How are you measuring the conversion time?  My guess is that if you are doing something like entering an ISR and then toggling a GPIO or spin-waiting on the ADCINT flag then toggling a GPIO then you are getting some additional cycles of overhead.  When you add one additional conversion, this overhead stays the same and you observe the expected delta in time.  

    Additional hint: if you are going to throw away the first conversion, I'm pretty sure you can use the minimum S+H time of ACQPS = 6.  

  • 0 in reply to Devin Cottier
    Prodigy 90 points

    Devin,

    Thanks for your reply. You are right, I am measuring the ADC conversion time by entering an ISR as described below.

    I have set up the ADC SOC by ePWM TBCTR equals zero. ePWM output is also set high when TBCTR equals zero.

    ADC EOC initiates the ADC ISR in which the the first instruction is GPIO = high.

    I am measuring ADC conversion time as time difference between low to high transition of ePWM output and low to high transition of GPIO.

    Whether this things could take long execution time as high as 20 ADC clock cycles ( or 40 CPU clock cycles) ?

    Requesting your expert advice on the same.

    With thanks & regards,

    Dipen

  • 0 in reply to Dipen Vachhani
    TI__Guru 60865 points

    Hi Dipen,

    The pure HW overhead for the ISR is at least 14 cycles: https://processors.wiki.ti.com/index.php/Interrupt_FAQ_for_C2000#ISR_Latency

    There is usually some additional code inserted by the compiler to setup the ISR.  You can step through the ISR using mixed C and assembly mode to see the generated instructions. 

    Finally, toggling the GPIO will take a few cycles: https://processors.wiki.ti.com/index.php/General_Purpose_IO_(GPIO)_FAQ_for_C2000#Q:_Toggling_of_the_GPIO_seems_slower_than_it_should_be

  • 0 in reply to Devin Cottier
    Prodigy 90 points

    Devin,

    Many thanks for your support and helping me in better understanding the Interrupt Latency as well as compiler action in building the code

    With thanks & regards,

    Dipen