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Hello,
I am new to the TI Piccolo Microcontrollers and I have a question about Data integrity in the Shared Memory between Control Law Accellerator and C28X Core.
Is there a way to ensure that one Core doesnt write to the same Data Section while the other Core Reads date from the Data Section.
Thanks to you
Markus
HI,
Is there a way to ensure that one Core doesnt write to the same Data Section while the other Core Reads date from the Data Section.
These are single port RAMs and hardware has arbitration logic to make sure only one access goes to RAM block. So data integrity is taken care by hardware.
Regards,
Vivek Singh
Thank you for your reply.
I guess you refer to section 3.11.1.5 of the Technical Reference Manual. Ist that right?
Thanks
Markus
Hi Markus,
I guess you refer to section 3.11.1.5 of the Technical Reference Manual. Ist that right?
That is correct.
Regards,
Vivek Singh