LAUNCHXL-F280049C: PGA gain

With a 1.65v bias on each PGA_IN, gain (x3) counts for ADCA=4063, ADCB=4055, ADCC=4059. That is no where close to 1.65v center (2048), DAC input bias should set the PGA_OUT center (1.65v) but not 3.3292vdc (-21A) as it was configured for SDK FOC. Also channel offsets are a bit uneven since the HAL_offset calculation can never run as it hangs forever, seemingly from calls to Sys_CtlDelay() . 

That said the USER_ADC_FULL_SCALE_CURRENT_A is not setting ADC peak (42.843A), offsets being -21A for each channel. Offsets are considered ADC +/- counts derived from mid supply +1.65v (2048) defined by equation 24 SPRUHJ1H–January 2013–Revised June 2019. The 0.820mV is the shunts CM differential, not the 1.65v input bias to PGA_IN.

So the INA240A1 with even 5mohm shunt (32A FS) using external DACA=1.65v for REF1/2 thus proves SDK user current scale factor is nonsense as it was designed. That is why the INA240 set mid supply 1.65v does not work with the SDK nor will any external differential amplifier that sets mid supply  1.65v output as it sets the correct center the PGA's x12 or x3 gain does not accomplish. The PGA outputs fall below any fixed ADC center of which only benefits the boostXL-drv8320rs and no customers DC inverter that sets a proper 1.65v center ADC threshold! Seemingly BoostXL never tripped CMPSS DCA/B or ePWM Tripin,7,8,9 and no OC condition ever occurs via PGA's front end current monitors. That can not be said for INA240 which easily trips faults in the CMPSSx for proper DC inverter protection.

PGA_IN gain (x3) 1.65v and PGA_OUT rails 3v3:

GI,

Gl said:

A1: PGA output analog signals seem to zero cross (R19, R22, R25 removed), J5 pins 45, 46, 48 are disconnected.

A2: 0R was chosen for R26, R27 PGA_GND since (Rgnd=10k for x3 gain) Fig. 8-12.

I am unsure what your are referring to by "A1" and "A2". When you are referencing these component numbers, are you referring to components that are on the 8320RS boosterPack? If so, it is unclear to me why you chose to modify the board that way.

Gl said:

1. Please elaborate how does A2 effect PGA output to center 1.65v per formula (yellow box) showing x3 gain?

Formula (yellow box) Fig. 8-12 shows 2*Vbipolar (+/-0.820mv) + Vref (1.65v) = Adcin (3v3).

Again unclear on what A2 is, but the PGA is centered around 1.65 at a gain of 12. This is done by setting the DAC at a value of 1.65 and using a voltage divider(divided by 12 or about 0.137V) so that the signal after amplified by the PGA is again centered at 1.65. If you wish to change to use another gain setting modify the voltage divider accordingly.

Gl said:

3. Will the PGA output (Vadcin) center at (1.65v) as the formula shows for PGA gain set x3?

Well, we had to choose something, if you can amplify the signal 12x without clipping then that is the best granularity you will have. This also results in a smaller ohm shunt resistor.

I have asked for specific feedback on 4 and 5. And will provide accordingly.

As for your second post I didn't see any questions, however yes it appears that the code in questions and am not sure how I can assist. Thanks for the feedback? It seems safe to assume that the code was probably developed for the DRV8320RS, which would explain why it works with that hardware. If a customer were to change the design to use an external amplifier with a different gain and possibly even a different biasing scheme... Then, yeah, I agree it would be bonkers to assume scale factor would remain the same.

Please let me know if there is anything else I can help you with.

Regards,
Cody

Cody Watkins said:

I am unsure what your are referring to by "A1" and "A2".

Answers 1/2 from original question of last thread (link) top of this thread.

Cody Watkins said:

but the PGA is centered around 1.65 at a gain of 12.

Seemingly that PGA_OUT (x12) center is not occurring Fig.8-12 since the INA240 centered 1.65v is tripping CMPSS faults EST_OL no matter the shunt (40mV/A) or (100mV/A) in the adjusted SF per formulas SPRUHJ1H. Otherwise the PGA is centered yet CMPSS were not tripping any PWM fault due to incorrect SW configurations. Either way patches were posted and no updates to the SDK have been made. That my friend after reported boostxl-drv8320rs fire is simply ignorant behavior on TI's behalf. One point of the forum customers to report hazardous issues so TI engineers can address them. 

Cody Watkins said:

Again unclear on what A2 is, but the PGA is centered around 1.65 at a gain of 12.

Yet at (x3) it is supposed to produce unity gain as the ADC buffer datasheet claims possible but produced the ADC register counts shown above. The trouble seem to be PGA_OUT may be centered 1.65v but the output is NOT AC. The inverting input (-IN) has feed back gain x12 (Rout 27k), Rgnd (2.5k) tied to R27. So PGA_OUT signal rides on top >1.65v positive direction only, no AC signal is produce. The INA240 produces an AC wave for the SDK (FIC) as outlined in SPRUHJ1H and some body at TI missed this issue. It explains why the boostxl-drv8320rs caught on fire during FW field weakening, negative current is inject into the air gap of the stator. That FW mode did not speed the motor rather it made the DC supply take a dive every time it was enabled since there was no negative current being reported by the PGA. Sinusoidal current waveform and proper CMPSSx shut down of ePWM module drive outputs is imperative for all custom and TI motor control designs.

CH2: INA240 AC current wave form, please show us (post) the capture from PGA_OUT of the same current ramp up prior to EST_OL.

Cody Watkins said:

Then, yeah, I agree it would be bonkers to assume scale factor would remain the same.

The scale factors were changed to reflect our custom HW, the entire point of the launch pad program seems to be lost if the INA240 can't work with or for the SDK or launchXL, take your pick they both fail. I say that heavy heartted after 2 weeks of TS since the EK-TM4c1294XL works with this same DC inverter and INA240 outputs are now centered 1.65v to match PGA_IN bias, PGA bypassed of course. Last ditch effort was to use DACA to lower INA Vref center below 1.65v, fails to make any difference.

we attempted to use the PGA gain (x3) as a unity buffer shown Fig.8-12 and x49c datasheet claims possible. The CCS debug results are posted above but idea for ADC buffer is to offset phase margin, impedance match analog source Rs as shown below. Why does this not work even when R27/R27 were removed or left in place the output count rails 3v for 1.65v input? What has to be done to make this buffer work with PGA?

Cody Watkins said:

f a customer were to change the design to use an external amplifier with a different gain and possibly even a different biasing scheme... Then, yeah, I agree it would be bonkers to assume scale factor would remain the same.

Seemingly you have missed the point the launch pad systems are not simply to sell Non FCC approved designs to the community. The kits have to follow dated guide lines as outlined in SPRUHJ1H–January 2013–Revised June 2019. Or update facts surrounding any changes that were made to kits that render written documents no longer valid. It seems that was not done and a conundrum is about to unfold as it is here!

This is how the INA240 output looks when (-IN) is tied to (Rgnd=10k) as in how the PGA_GND is tied to (Rgnd=2.5k) via R27/26 0R. Of course CH2 represents trapezoidal current wave but the point is the signal is mostly positive in this differential amp configuration. Seemingly the PGA_OUT is producing 1/2 wave and strips the bottom half of wave form as shown below CH2. 

GI,

Simply put I don't understand your system. Please answer a few questions to help me help you.

What hardware are you using? Provide any part numbers if possible, and describe any customer hardware.

What software solution are you using? What hardware was it designed for? 

It seems like you are prototyping, what will your endsystem look like? An F280049C conected to a DRVxx? with current feedback coming from an INA240?

Thanks,
Cody 

Cody Watkins said:

Simply put I don't understand your system

Its simply a launch pad connected to a DC inverter custom test unit. Like I said several times our DC inverter works fine. However the PGA amps seemingly as configured are producing 1/2 wave in BoostXL-drv8320rs. Please confirm the PGA_OUT wave form is full sinusoidal, provide a recent capture for forum members to review.

If PGA's are producing 1/2 wave versus full wave (sinusoidal) that would explain for such a difference when INA240 attempts to replace PGA's or use them as input buffers. TI has made no effort to produce any kind of circuit analysis of the BoostXL for using x49c PGA's as current amps as configured. So it's a crap shoot the development kit can leverage custom hardware designs into production after seeing failures of both ours and yours.

The one difference being the SDK (FOC) relied on Tz2 from the BoostXL and omitted full/proper configuration for the DC comparator fault circuits. If the BoostXL failed to raise OC detection the launch pad ePWM module would continue to drive it into complete destruction as it did. Again FW failed to inject negative current into the SPM air gap and eventually burned the BoostXL in blaze of glory.

No speed increase ever occurred several times FW was run, it only dragged down the phase voltages and rotor speed. If the PGA's are not producing sinusoidal output (negative cycles) that would explain why FW failed and BoostXL burned.

Cody Watkins said:

An F280049C conected to a DRVxx? with current feedback coming from an INA240?

What other configuration would you expect other than that and how does that even matter?

Cody Watkins said:

It seems like you are prototyping, what will your endsystem look like?

Have a custom PCB with TM4C1294 MCU and INA240's but considering C2000 migration for sinusoidal current detection. I highly doubt the PGA's can work at 150vdc SPM current feed back as front end current monitors, the MCU will suffer! We also need to use PGA's as analog input buffers to the ADC as stated TRM to remove external ADC buffers.  Yet the PGA does not seem to work as any kind of analog impedance matching device for external signals or R27/R26 are restricting the ability for PGA to act as a proper ADC buffer?

14.1 Programmable Gain Amplifier (PGA) Overview
The integrated PGA helps to reduce cost and design effort for many control applications that traditionally require external, standalone amplifiers. On-chip integration ensures that the PGA is compatible with the downstream ADC and CMPSS modules. Software selectable gain and filter settings make the PGA adaptable to various performance needs.

Gl said:

Please confirm the PGA_OUT wave form is full sinusoidal, provide a recent capture for forum members to review.

Unfortunately I currently do not have access to a LAUNCHXL-F280049C or a BOOSTXL-DRV8320RS, so I will not be providing any waveforms. The PGA's output will amplify what ever signal you give it. If that input is sinusoidal then it will come out sinusoidal on on the other side after a gain of your choosing is applied. Please note that the valid PGA output range is approximately VSSA to approximately VDDA, see the data sheet for an exact specification. 

Gl said:

TI has made no effort to produce any kind of circuit analysis of the BoostXL for using x49c PGA's as current amps as configured.

Gl said:

The one difference being the SDK (FOC) relied on Tz2 from the BoostXL and omitted full/proper configuration for the DC comparator fault circuits. If the BoostXL failed to raise OC detection the launch pad ePWM module would continue to drive it into complete destruction as it did. Again FW failed to inject negative current into the SPM air gap and eventually burned the BoostXL in blaze of glory.

Again its unclear exactly what you connected, modified, or did in the system so it is hard to tell what could have went wrong. Please note that the evaluation hardware that TI provides is solely for use by trained professionals in a laboratory environment. 

Gl said:

What other configuration would you expect other than that and how does that even matter?

If using the PGAs I would expect you to design your inverter feedback similar to what is done in BOOSTXL-DRV8320RS. Use a small current shunt, amplify that signal with the PGAs and sense it with the ADC. If you are wishing to use INA240 I would expect you to not use the PGAs because you already have an amplifier in your system.

Gl said:

I highly doubt the PGA's can work at 150vdc SPM current feed back as front end current monitors, the MCU will suffer!

The Absolute Maximum Rating for VIIN is ~4.6V, so yes I think it is safe to say 150Vdc will violate the datasheet specification. 

Gl said:

Yet the PGA does not seem to work as any kind of analog impedance matching device for external signals or R27/R26 are restricting the ability for PGA to act as a proper ADC buffer?

Interesting, what circuit have you tried to use to implement impedance matching using the PGA? The PGA does buffer the signal from the ADC sample and hold capacitor which should improve sampling error.

Regards,
Cody 

Hi Codly,

The problem in all this is the PAG_OUT is not centered 1.65v. The 7mohm shunt x12 gain gives us 84mV/A.  The SDK configured CMPSS2,4,6 as if PGA_OUT was 1/2 VDDA. A centered 1.65v ADC FS=19.64A is far from 42A FS as the SW was configured ADC for 1/2 VDDA. Needles to say the CMPSS low side was configured as if PGA_OUT was centered mid supply and inverted it's output. Again ADC full scale from center is only 19.64A, so the peak current is not 42A as configured and negative offset (-21A) is perhaps only reducing the full scale back to 21A peak? The BoostXL kit was designed to peak at 42A near VDDA but the -21A phase offsets make no sense and is not outlined SPRUHJ1H–January 2013–Revised June 2019!

Can you explain why this offset below was done or how it afects the ADC scale factor 42A. And how we might leverage the INA240A1 with TMS320F280049c for use with the SDK to confirm custom hardware as per LAB4 instructions?

//! \brief ADC current offsets for A, B, and C phases
#define IA_OFFSET_A    (-21.428)   // ~=0.5*USER_ADC_FULL_SCALE_CURRENT_A 
#define IB_OFFSET_A    (-21.428)   // ~=0.5*USER_ADC_FULL_SCALE_CURRENT_A
#define IC_OFFSET_A    (-21.428)

 The ADC current offset past MCU classes were considered amplifier current IQ bias. How does these new offset values differ from the standards outlined in SPRUHJ1H–January 2013–Revised June 2019? The SDK (FOC) and BoostXL-DRV8320rs ADC scale factors are not configured correctly even for PGA_OUT levels you have suggested. Past kits negative offset phase currents were IQ based bias values, roughly 5% of ADC full scale current and not 1/2 VDDA. That seems to explain how INA240 was so easily tripping CMPSS faults centered VDDA.

Was the peak phase current of the BoosXL-drv8320rs kit constrained to 21A and not 42A as user FS current is configured below and the SDK?

//! \brief Defines the maximum current at the AD converter
//!        BOARD_BSXL8320RS_REVA Gain=12 84mV/A, INA240 Gain=20 40mV/A
#define USER_ADC_FULL_SCALE_CURRENT_A     ((float32_t)(42.843))

Stay well in this pandemic!

Cody Watkins said:

Interesting, what circuit have you tried to use to implement impedance matching using the PGA? The PGA does buffer the signal from the ADC sample and hold capacitor which should improve sampling error.

Have you not been paying attention to above documented colored statements, suggest the PGA can buffer ADC input as the TRM outlines? The attached above single amplifier circuit is the typical front end buffer to ADC for impedance matching purpose. Yet the PGA can not be configured to buffer a mid VDDA input signal as it claims it can? Are you aware there was errata in the PGA fist two silicon releases? PGA: Output Filter Path is Not Supported 0, A, fixed in revision B. Mistakenly I had removed the 0R from the launch pad for filter use and could not scope probe the PGA_OUT.

Cody Watkins said:

Again its unclear exactly what you connected, modified, or did in the system so it is hard to tell what could have went wrong. Please note that the evaluation hardware that TI provides is solely for use by trained professionals in a laboratory environment

Most of these kits end up in shops just like ours and we don't wear white lab coats. Field weakening (FW) will not work correctly if negative current can not be developed in the air gap. How exactly is the PGA prodcing negative current samples if it is not centered from mid supply? All differential amplifiers require mid supply reference (1/2 VDDA) to produce and or detect bidirectional current samples. Otherwise they do not detect bidirectional current flow zero crossing the shunt in the opposite direction is clamped to ground. This is a lesson the INA240 teaches well.