CCS/TMS320F28377D: A strange question using F021 Flash API on F28377D

And please refer to below my source code.

#include "F28x_Project.h"
#include <string.h>
#include "flash_programming_c28.h" // Flash API example header file
#include "F021_F2837xD_C28x.h"

//
// Defines
//
#define WORDS_IN_FLASH_BUFFER 0xFF // Data/Program Buffer used for testing
// the flash API functions

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#define ramFuncSection ".TI.ramfunc"
#else
#define ramFuncSection "ramfuncs"
#endif
#endif

//
// Globals
//
#pragma DATA_SECTION(Buffer,"BufferDataSection");
uint16 Buffer[WORDS_IN_FLASH_BUFFER + 1];
uint32 *Buffer32 = (uint32 *)Buffer;

uint16 state = 0;

//
// Function Prototypes
//
void Example_Error(Fapi_StatusType status);
void Example_Done(void);
void Example_CallFlashAPI(void);

//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// Enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
InitSysCtrl();

//
// Unlock CSM
//
// If the API functions are going to run in unsecured RAM
// then the CSM must be unlocked in order for the flash
// API functions to access the flash.
// If the flash API functions are executed from secure memory
// then this step is not required.
//
//DcsmZ1Unlock();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
// InitGpio(); // Skipped for this example

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2802x_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
InitPieVectTable();

EINT;
//
// Copy time critical code and Flash setup code to RAM
// This includes InitFlash(), Flash API functions and any functions that are
// assigned to ramfuncs section.
// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
// symbols are created by the linker. Refer to the device .cmd file.
//
//memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

//
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
//
InitFlash();

//
// Gain pump semaphore
//

//SeizeFlashPump();
//
// Jump to RAM and call the Flash API functions
//

Example_CallFlashAPI();
}

//
// Example_CallFlashAPI - This function will interface to the flash API.
// Flash API functions used in this function are
// executed from RAM
//
#pragma CODE_SECTION(Example_CallFlashAPI, ramFuncSection);
void Example_CallFlashAPI(void)
{
uint32 u32Index = 0;
uint16 i = 0;

Fapi_StatusType oReturnCheck;
volatile Fapi_FlashStatusType oFlashStatus;
Fapi_FlashStatusWordType oFlashStatusWord;

while(1)
{
switch(state)
{
case 0:
break;
case 1: // FLASH Sector M data write

SeizeFlashPump();

//DINT;
EALLOW;

//
// This function is required to initialize the Flash API based on System
// frequency before any other Flash API operation can be performed
//
oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS, 200);

if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
//Example_Error(oReturnCheck);
}

//
// Fapi_setActiveFlashBank function sets the Flash bank and FMC for further
// Flash operations to be performed on the bank
//
oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
//Example_Error(oReturnCheck);
}

///////////////////////////////////////////////////////////

//
// Erase Sector C
//
oReturnCheck = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector,
(uint32 *)Bzero_SectorM_start);
//
// Wait until FSM is done with erase sector operation
//
while(Fapi_checkFsmForReady() != Fapi_Status_FsmReady){}
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
// If Erase command fails, use Fapi_getFsmStatus() function to get the
// FMSTAT register contents to see if any of the EV bit, ESUSP bit,
// CSTAT bit or VOLTSTAT bit is set (Refer to API documentation for
// more details)
//
//Example_Error(oReturnCheck);
}

//
// Read FMSTAT register contents to know the status of FSM after
// program command for any debug
//
oFlashStatus = Fapi_getFsmStatus();
if (oFlashStatus!=0)
{
//Example_Error(oReturnCheck);
}
//
// Verify that SectorL is erased. The Erase step itself does a
// verify as it goes. This verify is a 2nd verification that can be done.
//
oReturnCheck = Fapi_doBlankCheck((uint32 *)Bzero_SectorM_start,
Bzero_16KSector_u32length,
&oFlashStatusWord);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
// If Erase command fails, use Fapi_getFsmStatus() function to get the
// FMSTAT register contents to see if any of the EV bit, ESUSP bit,
// CSTAT bit or VOLTSTAT bit is set (Refer to API documentation for
// more details)
//
//Example_Error(oReturnCheck);
}

///////////////////////////////////////////////////////////

for(i=0; i <= WORDS_IN_FLASH_BUFFER; i++)
{
Buffer[i] = i;
}

for(i=0, u32Index = Bzero_SectorM_start;
(u32Index < (Bzero_SectorM_start + WORDS_IN_FLASH_BUFFER)) &&
(oReturnCheck == Fapi_Status_Success); i+= 8, u32Index+= 8)
{
oReturnCheck = Fapi_issueProgrammingCommand((uint32 *)u32Index,Buffer+i,
8,
0,
0,
Fapi_AutoEccGeneration);
while(Fapi_checkFsmForReady() == Fapi_Status_FsmBusy);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
//Example_Error(oReturnCheck);
}

//
// Read FMSTAT register contents to know the status of FSM after
// program command for any debug
//
oFlashStatus = Fapi_getFsmStatus();
if(oFlashStatus != 0)
{
//Check FMSTAT and debug accordingly
//Example_Error(oReturnCheck);
}

//
// Verify the values programmed. The Program step itself does a verify
// as it goes. This verify is a 2nd verification that can be done.
//
oReturnCheck = Fapi_doVerify((uint32 *)u32Index,
4, Buffer32+(i/2),
&oFlashStatusWord);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
//Example_Error(oReturnCheck);
}
}

//
// Enable ECC
//
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;

EDIS;// protect set

//
// Leave control over flash pump
//
ReleaseFlashPump();

//EDIS;
//EINT;
state = 0;
break;
case 2: // FLASH Sector M Erase

SeizeFlashPump();

Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0x0;
__asm(" RPT #7 || NOP");

//DINT;
EALLOW; // protect clear

// //
// // This function is required to initialize the Flash API based on System
// // frequency before any other Flash API operation can be performed
// //
// oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS, 200);
// if(oReturnCheck != Fapi_Status_Success)
// {
// //
// // Check Flash API documentation for possible errors
// //
// //Example_Error(oReturnCheck);
// }
//
// //
// // Fapi_setActiveFlashBank function sets the Flash bank and FMC for further
// // Flash operations to be performed on the bank
// //
// oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);
// if(oReturnCheck != Fapi_Status_Success)
// {
// //
// // Check Flash API documentation for possible errors
// //
// //Example_Error(oReturnCheck);
// }

//
// Erase Sector C
//
oReturnCheck = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector,
(uint32 *)Bzero_SectorM_start);
//
// Wait until FSM is done with erase sector operation
//
while(Fapi_checkFsmForReady() != Fapi_Status_FsmReady){}
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
// If Erase command fails, use Fapi_getFsmStatus() function to get the
// FMSTAT register contents to see if any of the EV bit, ESUSP bit,
// CSTAT bit or VOLTSTAT bit is set (Refer to API documentation for
// more details)
//
//Example_Error(oReturnCheck);
}

//
// Read FMSTAT register contents to know the status of FSM after
// program command for any debug
//
oFlashStatus = Fapi_getFsmStatus();
if (oFlashStatus!=0)
{
//Example_Error(oReturnCheck);
}
//
// Verify that SectorL is erased. The Erase step itself does a
// verify as it goes. This verify is a 2nd verification that can be done.
//
oReturnCheck = Fapi_doBlankCheck((uint32 *)Bzero_SectorM_start,
Bzero_16KSector_u32length,
&oFlashStatusWord);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
// If Erase command fails, use Fapi_getFsmStatus() function to get the
// FMSTAT register contents to see if any of the EV bit, ESUSP bit,
// CSTAT bit or VOLTSTAT bit is set (Refer to API documentation for
// more details)
//
//Example_Error(oReturnCheck);
}

//
// Enable ECC
//
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
__asm(" RPT #7 || NOP");

EDIS;// protect set

//
// Leave control over flash pump
//
ReleaseFlashPump();

//EDIS;
//EINT;
state = 0;
break;
case 3: // FLASH 0xFFFF dummy data write

SeizeFlashPump();

//DINT;
EALLOW;

//
// This function is required to initialize the Flash API based on System
// frequency before any other Flash API operation can be performed
//
oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS, 200);

if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
Example_Error(oReturnCheck);
}

//
// Fapi_setActiveFlashBank function sets the Flash bank and FMC for further
// Flash operations to be performed on the bank
//
oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
Example_Error(oReturnCheck);
}

for(i=0; i <= WORDS_IN_FLASH_BUFFER; i++)
{
Buffer[i] = i+2;
}

for(i=0, u32Index = Bzero_SectorM_start;
(u32Index < (Bzero_SectorM_start + WORDS_IN_FLASH_BUFFER)) &&
(oReturnCheck == Fapi_Status_Success); i+= 8, u32Index+= 8)
{
oReturnCheck = Fapi_issueProgrammingCommand((uint32 *)u32Index,Buffer+i,
8,
0,
0,
Fapi_AutoEccGeneration);
while(Fapi_checkFsmForReady() == Fapi_Status_FsmBusy);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//

}

//
// Read FMSTAT register contents to know the status of FSM after
// program command for any debug
//
oFlashStatus = Fapi_getFsmStatus();
if(oFlashStatus != 0)
{
//Check FMSTAT and debug accordingly
Example_Error(oReturnCheck);
}

//
// Verify the values programmed. The Program step itself does a verify
// as it goes. This verify is a 2nd verification that can be done.
//
oReturnCheck = Fapi_doVerify((uint32 *)u32Index,
4, Buffer32+(i/2),
&oFlashStatusWord);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
Example_Error(oReturnCheck);
}
}

//
// Enable ECC
//
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;

EDIS;// protect set

//
// Leave control over flash pump
//
ReleaseFlashPump();

//EDIS;
//EINT;
state = 0;
break;
default:
break;
}
}
}

//
// Example_Error - For this example, if an error is found just stop here
//
#pragma CODE_SECTION(Example_Error,ramFuncSection);
void Example_Error(Fapi_StatusType status)
{
//
// Error code will be in the status parameter
//
//__asm(" ESTOP0");
}

//
// Example_Done - For this example, once we are done just stop here
//
#pragma CODE_SECTION(Example_Done,ramFuncSection);
void Example_Done(void)
{
//__asm(" ESTOP0");
}

I set the flash.cmd file.
like this:
SECTIONS
{
.text : > FLASH, PAGE = 0, ALIGN(4)
.cinit : > FLASH, PAGE = 0, ALIGN(4)
.const : > FLASH, PAGE = 0, ALIGN(4)
.econst : > FLASH, PAGE = 0, ALIGN(4)
.pinit : > FLASH, PAGE = 0, ALIGN(4)
.switch : > FLASH, PAGE = 0, ALIGN(4)
}
But I coudn't solved it.

Edward,

Looks like you are executing Flash API functions from Flash.  Correct?

If you take a look at the linker command file used by the Flash API usage example (C2000Ware_x_xx_xx_xx\device_support\f2837xd\examples\dual\flash_programming\cpu01\flash_programming_cpu1_FLASH.cmd), you will notice that Flash API library and ramfuncs (or .TI.ramfunc) are grouped together and given a Flash load address and a RAM run address.

Can you try this and let me know if this fixes your issue?

Thanks and regards,
Vamsi

Edward,

As mentioned in Table 4-13. Wait Point Addresses for CPU1 of the TRM (http://www.ti.com/lit/ug/spruhm8h/spruhm8h.pdf), your application is ending up in ITRAP ISR.  

As I suggested earlier, please assign a Flash load address and RAM run address for ramfuncs and Flash API library.  And call memcpy() function before executing any of the Flash API functions or the ramfuncs code.

Thanks and regards,

Vamsi

Dear Vamsi

Really thanks for reply
As you see the upper code, I used memcpy functions.
like this:
#pragma CODE_SECTION(Example_CallFlashAPI, ramFuncSection);
void Example_CallFlashAPI(void)

the upper code was based on Flash API usage example (C2000Ware_x_xx_xx_xx\device_support\f2837xd\examples\dual\flash_programming\cpu01\flash_programming_cpu1_FLASH.cmd).

Thanks and regards,

Edward

Edward,

I see memcpy() is commented out in your code.  Please check.

Also, please take a look at the linker cmd file carefully.  Flash API library should have a load Flash address and RAM run address; I don't see this in your linker cmd file.

Thanks and regards,

Vamsi

Dear Vamsi

Thanks for reply

I'm checking your comment.

I attached below cmd file.

// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002

RAMGS01 : origin = 0x00C000, length = 0x002000
// RAMGS0 : origin = 0x00C000, length = 0x001000
// RAMGS1 : origin = 0x00D000, length = 0x001000

RAMGS23 : origin = 0x00E000, length = 0x002000
// RAMGS2 : origin = 0x00E000, length = 0x001000
// RAMGS3 : origin = 0x00F000, length = 0x001000

/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */

PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800

RAMLS0123 : origin = 0x008000, length = 0x002000
// RAMLS0 : origin = 0x008000, length = 0x000800
// RAMLS1 : origin = 0x008800, length = 0x000800
// RAMLS2 : origin = 0x009000, length = 0x000800
// RAMLS3 : origin = 0x009800, length = 0x000800

RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800

RAMGS4567891011 : origin = 0x010000, length = 0x008000
// RAMGS4 : origin = 0x010000, length = 0x001000
// RAMGS5 : origin = 0x011000, length = 0x001000
// RAMGS6 : origin = 0x012000, length = 0x001000
// RAMGS7 : origin = 0x013000, length = 0x001000
// RAMGS8 : origin = 0x014000, length = 0x001000
// RAMGS9 : origin = 0x015000, length = 0x001000
// RAMGS10 : origin = 0x016000, length = 0x001000
// RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12131415 : origin = 0x018000, length = 0x004000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

// EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
EMIF2_CS2n : origin = 0x00002000, length = 0x00001000

CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080

CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400

UPP_MSGRAMTX : origin = 0x006C00, length = 0x000100
UPP_MSGRAMRX : origin = 0x006E00, length = 0x000100
SDRAM : origin = 0x80000000, length = 0x10000000 /* 512Kx16 SDRAM */

}

SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB, PAGE = 0, ALIGN(4)
.pinit : > FLASHB, PAGE = 0, ALIGN(4)
.text : >> FLASHB | FLASHC | FLASHD | FLASHE, PAGE = 0, ALIGN(4)
codestart : > BEGIN, PAGE = 0, ALIGN(4)

/* Allocate uninitalized data sections: */
.stack : > RAMM1, PAGE = 1
#ifdef CPU1
// .ebss : >> RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3, PAGE = 1
.ebss : > RAMLS0123, PAGE = 1
// .ebss : > RAMGS01, PAGE = 1
Filter_RegsFile : > RAMLS0123, PAGE = 1
// Filter_RegsFile : > RAMGS01, PAGE = 1
#endif

#ifdef CPU2
.ebss : > RAMLS0123, PAGE = 1
// .ebss : > RAMGS01, PAGE = 1
Filter_RegsFile : > RAMLS0123, PAGE = 1
// Filter_RegsFile : > RAMGS01, PAGE = 1
#endif
.esysmem : > RAMD1, PAGE = 1
.cio : > RAMD1, PAGE = 1

/* Initalized sections go in Flash */
.econst : >> FLASHF | FLASHG | FLASHH, PAGE = 0, ALIGN(4)
.switch : > FLASHB, PAGE = 0, ALIGN(4)

.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.farbss : > SDRAM, PAGE = 1

SHARERAMGS4 : > RAMGS4567891011, PAGE = 1
SHARERAMGS15 : > RAMGS12131415, PAGE = 1
// EXDRAM : > SDRAM, PAGE = 1
// SHARERAMGS0 : > RAMGS0, PAGE = 1
// SHARERAMGS1 : > RAMGS1, PAGE = 1
// SHARERAMGS2 : > RAMGS2, PAGE = 1
// SHARERAMGS3 : > RAMGS3, PAGE = 1
// SHARERAMGS4 : > RAMGS4, PAGE = 1
// SHARERAMGS5 : > RAMGS5, PAGE = 1
// SHARERAMGS5 : > RAMGS5, PAGE = 1
// SHARERAMGS6 : > RAMGS6, PAGE = 1
// SHARERAMGS7 : > RAMGS7, PAGE = 1
// SHARERAMGS8 : > RAMGS8, PAGE = 1
// SHARERAMGS9 : > RAMGS9, PAGE = 1
// SHARERAMGS10 : > RAMGS10, PAGE = 1

// SHARERAMGS11 : > RAMGS11, PAGE = 1
// SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// SHARERAMGS14 : > RAMGS14, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// SHARERAMGS15 : > RAMGS15, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
#ifdef CPU1
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD | FLASHE,
RUN = RAMGS01,
// RUN = RAMLS0 | RAMLS1 | RAMGS14 | RAMGS15,//수정포인트
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
ramfuncs : LOAD = FLASHD | FLASHE,
RUN = RAMGS01,
// RUN = RAMLS0 | RAMLS1 | RAMGS14 | RAMGS15,//수정포인트
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#endif
#endif //END #ifdef CPU1

#ifdef CPU2
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD | FLASHE,
RUN = RAMGS23,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
ramfuncs : LOAD = FLASHD | FLASHE,
RUN = RAMGS23,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#endif
#endif //END #ifdef CPU2

/* CLA specific sections */
Cla1Prog : LOAD = FLASHD, //수정포인트
RUN = RAMLS2 | RAMLS3, //수정포인트
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(4)

CLADataLS4 : > RAMLS4, PAGE = 1 //수정포인트
CLADataLS5 : > RAMLS5, PAGE = 1 //수정포인트
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1

#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS5, PAGE = 1

.scratchpad : > RAMLS5, PAGE = 1
.bss_cla : > RAMLS5, PAGE = 1
.const_cla : LOAD = FLASHD,
RUN = RAMLS5,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 1
#endif //CLA_C

#ifdef CPU1
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
#endif

#ifdef CPU2
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
#endif
/* The following section definition are for SDFM examples */
// Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
// Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
// Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
// Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
// Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Thanks and regards,

Edward

Edward,

In your linker cmd file, I don't see the Flash API library mapped to Flash for load and RAM for run. 

Please go through the linker cmd file that I suggested earlier and correct your linker cmd.

Also, please do not copy all of your code and linker cmd in the body of the post. Instead, please attach the docs.  I did not review your code.

Thanks and regards,
Vamsi

Dear Vamsi

Alright. I'm trying your suggestions.

And I attached the cmd file. please confirm the refer file.

How mapping the Flash API library to Flash and RAM? Please tell me for advice.

28377D_FLASH.zip

Thanks and regards,
Edward

Edward,

If you take a look at the linker command file used by the Flash API usage example  (C2000Ware_x_xx_xx_xx\device_support\f2837xd\examples\dual\flash_programming\cpu01\flash_programming_cpu1_FLASH.cmd), you will see that F021_API_F2837xD_FPU32.lib is mapped to FLASHD for load and RAMLS03 for run.  See below.  I don't see this in your linker cmd file that you shared.     

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
GROUP
{
.TI.ramfunc
{ -l F021_API_F2837xD_FPU32.lib}

} LOAD = FLASHD,
RUN = RAMLS03,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0
#else
GROUP
{
ramfuncs
{ -l F021_API_F2837xD_FPU32.lib}

} LOAD = FLASHD,
RUN = RAMLS03,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0
#endif
#endif

Thanks and regards,
Vamsi

Dear Vamsi
I modified the link file on your suggestion. then I felt solve this issue. but when I tested it, it occurred another situation.
The flash writes and erase was working well and after 2~3minite, the board occurred reset function.

I don't understand why it occurred the reset function.

I am really helpful and thanks for your answer.

Thanks and best regards,

Edward