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TMS320F28377D: The difference between DB_ACTV_HIC and DB_ACTV_HI when initial ePWM

Tobby Guo
Intellectual 770 points
Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

Hi:

when USE DB_ACTV_HIC to initial ePWM , a unexpected  plus occur on EPWM1B when execute initial, the display as below:

CH1: Trigger signal  CH2:EPWM1B,      EPWM1A is always low( do not display on scope)  

the initial code:


EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET;

EPwm1Regs.AQSFRC.bit.RLDCSF = 3; //The active register load immediately
EPwm1Regs.AQCSFRC.bit.CSFA = FORCE_LOW; //FORCE the EPWM2A output LOW
EPwm1Regs.AQCSFRC.bit.CSFB = FORCE_HIGH; //FORCE the EPWM2B output HIGH

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; //EPWMxA In is the source for rising-edge delayed signal.
EPwm1Regs.DBCTL.bit.DEDB_MODE = 0;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; //Active high complementary (AHC). EPWMxB is inverted.
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //Enable dead band time configuration
EPwm1Regs.DBCTL.bit.OUTSWAP = 0; 
EPwm1Regs.DBRED.all = EPWM1_DBRED;
EPwm1Regs.DBFED.all = EPWM1_DBFED;

then change to DB_ACTV_HI, the display as below:

 

CH1: Trigger signal  CH2:EPWM1B,      EPWM1A is always low( do not display on scope)  

the initial code:


EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.AQCTLB.bit.CBU =AQ_SET ;
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;

EPwm1Regs.AQSFRC.bit.RLDCSF = 3; //The active register load immediately
EPwm1Regs.AQCSFRC.bit.CSFA = FORCE_LOW; //FORCE the EPWM2A output LOW
EPwm1Regs.AQCSFRC.bit.CSFB = FORCE_LOW; //FORCE the EPWM2B output HIGH

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; //EPWMxA In is the source for rising-edge delayed signal.
EPwm1Regs.DBCTL.bit.DEDB_MODE = 0;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; //Active high complementary (AHC). Neither EPWMxA nor EPWMxB is inverted (default).
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //Enable dead band time configuration
EPwm1Regs.DBCTL.bit.OUTSWAP = 0; 
EPwm1Regs.DBRED.all = EPWM1_DBRED;
EPwm1Regs.DBFED.all = EPWM1_DBFED;

Between the two plans ,the first give EPWM1B force high then inverter in  DBCTL[POLSEL], the second give EPWM1B force low then Neither EPWMxA nor EPWMxB isinverted  in  DBCTL[POLSEL].

The initial code is execute in sequence, the two plans  should have same output on EPWM1B,  why the fisrt have a 20us high pluse.

Addition information:

fpwm:20kHz  

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

Thanks

  • 0
    Intellectual 770 points

    Supplement：

    In the first plan , EPWM1A and 1B have same value and action, use DBCTL[POLSEL] to inverte EPWM1B, and use DBRED and DBFED to set DEADBAND time. 

    In the second plan , EPWM1A and 1B have same value and Complementary action, use +/- Dtime value  to set DEADBAND time. 

    Prefer the first plan ,but can not  accept the unexpected high pluse when initial.

    Thanks

  • 0 in reply to Tobby Guo
    TI__Mastermind 24095 points

    Hi,

    Can you refer this post and let me know if it helps?
    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/838289?TMS320F280049-Active-high-complementary-PWMs This seems to refer to the same issue you've explained here, if i understand correctly.

  • 0 in reply to Subrahmanya
    Intellectual 770 points

    HI：

    Thanks for you reply.

    As my post above , i use DB_ACTV_HI to dismiss the unexpected plus.But about DB_ACTV_HIC,  before EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI, i set the EPwm1Regs.AQCSFRC.bit.CSFA = FORCE_LOW;   EPwm1Regs.AQCSFRC.bit.CSFB = FORCE_HIGH;.

    The initial code is execute in sequence, so i think the high plus shouid be the execute time of the two code between . The execute time should less than 20us , why the high plus have 20us

    the post you suggest is less than  20us

  • 0 in reply to Tobby Guo
    TI__Mastermind 24095 points

    Hi,

    The deadband configuration, be it active high or active high complimentary (edge based configuration/delay) would come into effect upon PWM edge occurrence.
    EPwm1Regs.AQCSFRC.bit.CSFA/B forces would take effect immediately. It's not clear to me why you had to do continuous software force in the initial configuration.
    Also, in case you use CSFA/B but NOT configure PWM to be EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI and only use DB_ACTV_HIC, do you still see the same results?
    Can you also cross check configuration w.r.t. example below?
    C:\ti\c2000\C2000Ware_2_01_00_00\device_support\f2837xd\examples\cpu1\epwm_deadband\cpu01
    EPWM3 uses DB_ACTV_HIC.

  • 0 in reply to Subrahmanya
    Intellectual 770 points

    Thanks for your reply.