Tool/software: Code Composer Studio
Hello ladies and gentlemen,
(TL;DR version below) I'm trying to implement a peak current-mode control for a boost converter on the LAUNCHXL-F280049C. I am using one of the analog comparator submodules (Cmpss2) to measure a voltage supplied by a DC voltage source to the pin J7-69 (ADCINA3 / PGA2_IN). This voltage is fed to the positive input of the COMPH comparator (CMP2_HP2) and compared to the value specified in the Cmpss2Regs.DACHVALS register on the negative comparator input. The output of the comparator is then routed to the Digital Compare submodule via the EPWM X-Bar. The signal is muxed to DCAH using the EPwm1Regs.DCTRIPSEL register. I have set the condition for a DCAEVT1 event to occur (which forces my EPWM1A output "low") within the EPwm1Regs.TZDCSEL register to be "DCAH = high, DCAL = don't care". This means that the analog comparator output has to be "high" for a DCAEVT1 to occur, if I am not mistaken.
Now, after starting the program on my F280049C, the EPWM1A output is constantly "low" after applying the above configurations. I have set the value in the Cmpss2Regs.DACHVALS register to 1024 for testing, which should require the positive input voltage to be about (3.3V * 1024 / 4096) = 0.825V to create a "high" analog comparator output and therefore a Digital Compare event, which in turn pulls the PWM "low". However, as I said, the PWM output is constantly "low", whether I am applying a voltage above or below 0.825V.
If I choose a different condition in the EPwm1Regs.TZDCSEL register, or if I disable the analog comparator so no signal can be passed to DCAH, then DCAEVT1 events do not happen and my PWM output looks as usual. So, looking at Figure 18-48 on page 1872 in the reference manual (sprui33c), I am now assuming that there must be an issue with the DCAH or DCAL signals and how they create a DCAEVT1 event. The TZFLG[DCAEVT1] register shows that, indeed, an event has happened, but I am unsure what exactly happens before that.
Interestingly, though I don't know if that helps solving my issue: If I set EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 1 so that the condition "DCAH = low, DCAL = don't care" creates a DCAEVT1 event, no event happens regardless of the voltage fed to the positive analog comparator input. If I then force a DCAEVT1 using the EPwm1Regs.TZFRC register, the PWM constantly ouputs "low" (as can be expected), this change can not be reverted even after clearing the corresponding TZFLG flag or changing the EPwm1Regs.TZDCSEL.bit.DCAEVT1 value, so the PWM output stays "low".
TL;DR: So what I want to achieve now is that the EPWM1A output is only pulled "low" when the voltage supplied to the analog comparator is above 0.825V (for instance) and that the PWM output continues to behave as usual as soon as the voltage decreases back to 0.825V or below. I hope the parts of my code below will help finding the mistake I probably made:
void initPWM()
{
EALLOW;
// Define PWM period and duty cycle
EPwm1Regs.TBPRD = Tp;
EPwm1Regs.CMPA.bit.CMPA = duty*EPwm1Regs.TBPRD;
// Various PWM settings
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up only mode
EPwm1Regs.TBCTL.bit.PRDLD = 1; // TBPRD can only be written directly
EPwm1Regs.TBCTL.bit.CLKDIV = 0; // PWM Clk Divider = 1
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // High Speed PWM Clk Divider = 1
EPwm1Regs.TBCTL.bit.FREE_SOFT = 2; // Counter never stops
// Action Qualifier settings
EPwm1Regs.AQCTLA.bit.PRD = 2; // Output "High" when CNT = TPRD
EPwm1Regs.AQCTLA.bit.CAU = 1; // Output "Low" wenn CNT = CMPA
// Digital Compare and Trip Zone settings
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3; // Digital Compare A High Input (TRIPIN4 is muxed to DCAH)
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0; // Source is DCAEVT1 signal
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // Source is passed through asynchronously
EPwm1Regs.TZSEL.bit.DCAEVT1 = 1; // Enable DCAEVT1 as a cycle-by-cycle trip source for ePWM1
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2; // DCAEVT1 caused when: DCAH = high, DCAL = don't care
EPwm1Regs.TZCTL.bit.DCAEVT1 = 2; // Force EPWM1A output "low" when a DCAEVT1 event occurs
EDIS;
}
void initComparator(void)
{
EALLOW;
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL = 2; // Select CMP2_HP2 (positive comparator input)
CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; // Enable CMPSS2 (Comparator 2) Clock
Cmpss2Regs.COMPCTL.bit.COMPDACE = 1; // Comparator 2 / DAC enable
Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = 0; // Negative comparator input is fed internally by DACHVALS
Cmpss2Regs.DACHVALS.bit.DACVAL = 1024; // Negative comparator input value: DACVAL*3.3V/4096 in volts
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 1; // Comparator 2 output (CMPSS2.CTRIPH) is muxed to TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1; // Enable MUX2
EDIS;
}
Any help is appreciated and I am greatly looking forward to your answers.
Kind regards,
Willem
