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Original question:

TMS320F28069: SCI FIFO Buffer Management

TMS320F28035: SCI FIFO levels confusion

Rajesh Kulkarni52
Intellectual 255 points
Part Number: TMS320F28035

Hi,

I have a pretty simple query. I am working a project which needs to me to use the SCI FIFO on TMS320F28035 . But referring to the SPRUI10 technical reference manual (www.ti.com/.../sprui10.pdf) I was a bit confused as to how many levels of FIFO does the chip offer.

On page 728 it is mentioned that the SCI peripheral transmitter and receiver each offer 4 level deep FIFO. But on page 739 point 6 in SCI FIFO Description  says "Transmit and receive buffers are supplemented with two 16-levelFIFOs" . And on the very next page 729. In the logic diagram its represented as 16 x 8 bit FIFO with 16 levels.

I am not entirely sure if its only 4 level deep. May be I am misinterpreting something .

Thank you and be safe !

Rajesh.

  • 0
    TI__Genius 17315 points

    Rajesh,

    The F28035 SCI has 4-level deep FIFOs.  There is a document filter error (for 4 vs. 16) in the TRM and I will have this corrected.  The value is correct on the data sheet (page 48 and 101):

    http://www.ti.com/lit/sprs584

    It is also correct in the C2000 Real-Time Control Peripherals Reference Guide (page 40):

    http://www.ti.com/lit/spru566

    Thanks for pointing this out, and stay safe, too.  I hope this answers your question and if so, please click the green "Verified Answer" button. Thank you.

    - Ken