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I generated 50% of the two 517kHz PWM signals through HRPWM. Use the same ePWM module. Then, it was found that one of the PWM signals was unstable. is it right?
void Setup_HRPWM_UpDownCount(uint32_t base1, uint16_t pwm_period_ticks, uint16_t red_ns, uint16_t fed_ns){ uint16_t status; // period = (((float32_t)100*1000000) / ((float32_t)700*1000)); // pwmPeriod_ticks = (uint32_t)period >> 1; // P_Fra = (int16_t)((float)__fracf32(period) * 256); // C_Fra = (int16_t)((float)__fracf32(period * 0.5) * 256 + 0.5); // // uint32_t temp; // // temp = ((uint32_t)(((float32_t)((float32_t)100*1000000/(float32_t)715*1000) * (float32_t)TWO_RAISED_TO_THE_POWER_SIXTEEN)))>> 1; // // pwmPeriod_ticks = temp & 0xFFFFFF00; status = SFO_INCOMPLETE; // // Calling SFO() updates the HRMSTEP register with calibrated // MEP_ScaleFactor. // HRMSTEP must be populated with a scale factor value prior to enabling // high resolution period control. // while(status == SFO_INCOMPLETE){ status = SFO(); if(status == SFO_ERROR) { asm(" ESTOP0"); } // steps/coarse step exceeds maximum of 255. }
EPWM_setEmulationMode(base1, EPWM_EMULATION_FREE_RUN); // Time Base SubModule Registers EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_SHADOW_LOAD); EPWM_setTimeBaseCounter(base1, 0); EPWM_disablePhaseShiftLoad(base1); EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP_DOWN); EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); // EPWM_setSyncOutPulseMode(base1, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO); EPWM_setActionQualifierShadowLoadMode(base1, EPWM_ACTION_QUALIFIER_A, EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO); EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierShadowLoadMode(base1, EPWM_ACTION_QUALIFIER_B, EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO); EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); // // Clear AQCTLA, B and Deadband settings settings // EALLOW; HWREGH(base1 + EPWM_O_AQCTLA) = 0x0000; HWREGH(base1 + EPWM_O_AQCTLB) = 0x0000; HWREGH(base1 + EPWM_O_DCBCTL) = 0x0000; EDIS; EPWM_setActionQualifierSWAction(base1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH); EPWM_forceActionQualifierSWAction(base1, EPWM_AQ_OUTPUT_B); EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); // Active high complementary PWMs - Set up the deadband // EPWM_setRisingEdgeDelayCountShadowLoadMode(base1, EPWM_RED_LOAD_ON_CNTR_ZERO); // EPWM_setFallingEdgeDelayCountShadowLoadMode(base1, EPWM_FED_LOAD_ON_CNTR_ZERO); // EPWM_setDeadBandCounterClock(base1, EPWM_DB_COUNTER_CLOCK_HALF_CYCLE); // EPWM_setRisingEdgeDelayCount(base1, red_ns); // EPWM_setFallingEdgeDelayCount(base1, fed_ns); // // EPWM_setDeadBandDelayMode(base1, EPWM_DB_RED, true); // EPWM_setDeadBandDelayMode(base1, EPWM_DB_FED, true); // EPWM_setRisingEdgeDeadBandDelayInput(base1, EPWM_DB_INPUT_EPWMA); // EPWM_setFallingEdgeDeadBandDelayInput(base1, EPWM_DB_INPUT_EPWMB); // EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH); // EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); HRPWM_setCounterCompareShadowLoadEvent(base1, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setMEPEdgeSelect(base1, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE); HRPWM_setMEPControlMode(base1, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setCounterCompareShadowLoadEvent(base1, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO); HRPWM_setMEPEdgeSelect(base1, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE); HRPWM_setMEPControlMode(base1, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setChannelBOutputPath(base1, HRPWM_OUTPUT_ON_B_NORMAL); HRPWM_enableAutoConversion(base1); HRPWM_enablePeriodControl(base1); //------------------------------------------------------------------------------------------------------------------------------------------------------------- // Global update setting //------------------------------------------------------------------------------------------------------------------------------------------------------------- EPWM_enableGlobalLoadRegisters(base1, EPWM_GL_REGISTER_CMPA_CMPAHR | EPWM_GL_REGISTER_TBPRD_TBPRDHR |
EPWM_GL_REGISTER_TBPRD_TBPRDHR | EPWM_GL_REGISTER_DBRED_DBREDHR |
EPWM_GL_REGISTER_DBFED_DBFEDHR | EPWM_GL_REGISTER_CMPB_CMPBHR |
EPWM_GL_REGISTER_AQCTLA_AQCTLA2 | EPWM_GL_REGISTER_AQCTLB_AQCTLB2); EPWM_setGlobalLoadTrigger(base1, EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO); EPWM_enableGlobalLoadOneShotMode(base1); EPWM_enableGlobalLoad(base1); // Dead time bypassed for test // EPWM_setDeadBandDelayMode(base1,EPWM_DB_RED,0); //EPWMx, DBCTL bit1 = 0b --> S1=0 --> EPWMxA Dead time bypassed // EPWM_setDeadBandDelayMode(base1,EPWM_DB_FED,0); //EPWMx, DBCTL bit0 = 0b --> S0=0 --> EPWMxB dead time bypassed //------------------------------------------------------------------------------------------------------------------------------------------------------------- // EPWM_setGlobalLoadOneShotLatch(base1); //GLDCTL2 bit0 OSHTLD = 1b, Global load strob }
int main(void){ inital...... Setup_HRPWM_UpDownCount(PWM_BASE, pwm_period_ticks, 100, 100); temp = (uint32_t)(1e8 / 5.17e5 * TWO_RAISED_TO_THE_POWER_SIXTEEN) >> 1; temp &= 0xFFFFFF00; P_cmp = temp >> 1; EALLOW; HWREG(PWM_BASE + HRPWM_O_TBPRDHR) = temp; HWREG(PWM_BASE + HRPWM_O_CMPB) = P_cmp; EDIS; EPWM_setGlobalLoadOneShotLatch(PWM_BASE); }
Hi,
Before we validate your configuration could you please check the following example? Do you observe any unstable outputs?
C:\ti\c2000\C2000Ware_3_01_00_00\device_support\f2837xd\examples\cpu1\hrpwm_prdupdown_sfo_v8
C:\ti\c2000\C2000Ware_3_01_00_00\device_support\f2837xd\examples\cpu1\hrpwm_deadband_sfo_v8