- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
Tool/software: Code Composer Studio
hi,
we have a question about PWM plus loss.
we used a 28377 for phase shift full bridge, Up and Down count mode, EPwm8Regs.TBPHS.bit.TBPHS range is from 0~400.
we found EPWM8 would loss pwm plus sometime. here is our code, could you help to review it and give us some suggestion?
EPwm7Regs.TBCTR = 0;
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm7Regs.TBCTL.bit.CLKDIV = 0;
EPwm7Regs.TBCTL.bit.CTRMODE = 2;
EPwm7Regs.TBCTL.bit.PHSEN = 0;
EPwm7Regs.TBCTL.bit.SYNCOSEL =1;
EPwm7Regs.TBCTL.bit.PRDLD= 0;
EPwm7Regs.AQCTLA.bit.CAU = 2;
EPwm7Regs.AQCTLA.bit.PRD = 1;
EPwm7Regs.AQCTLB.bit.CBD = 2;
EPwm7Regs.AQCTLB.bit.ZRO = 1;
EPwm7Regs.AQSFRC.bit.RLDCSF= 3;
EPwm7Regs.AQCSFRC.bit.CSFA = 1;
EPwm7Regs.AQCSFRC.bit.CSFB = 2;
EPwm7Regs.DBCTL.all = 0;
EPwm7Regs.CMPCTL.bit.SHDWAMODE = 0x0;
EPwm7Regs.CMPCTL.bit.SHDWBMODE = 0x0;
EPwm7Regs.CMPCTL.bit.LOADAMODE = 0x0;
EPwm7Regs.CMPCTL.bit.LOADBMODE = 0x0;
EPwm7Regs.TBPRD = 1169;
EPwm7Regs.TBPRDHR = (151<< 8);
EPwm7Regs.CMPA.bit.CMPA = 120;
EPwm7Regs.CMPB.bit.CMPB = 1169- 120;
EPwm7Regs.DBRED = 800;
EPwm7Regs.DBFED = 800;
EPwm7Regs.TBPHS.bit.TBPHS = 0;
EALLOW;
EPwm7Regs.HRCNFG.bit.EDGMODE = 3;
EPwm7Regs.HRCNFG.bit.CTLMODE = 0;
EPwm7Regs.HRCNFG.bit.HRLOAD = 2;
EPwm7Regs.HRCNFG.bit.SELOUTB = 0;
EPwm7Regs.HRCNFG.bit.AUTOCONV = 1;
EPwm7Regs.HRCNFG.bit.SWAPAB = 0;
EPwm7Regs.HRCNFG.bit.EDGMODEB = 3;
EPwm7Regs.HRCNFG.bit.CTLMODEB = 0;
EPwm7Regs.HRCNFG.bit.HRLOADB = 2;
EPwm7Regs.HRPCTL.bit.HRPE = 1;
EPwm7Regs.TBCTL.bit.SWFSYNC = 1;
EDIS;
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 0x0;
GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 0x0;
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0x1;
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0x1;
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;
EDIS;
// Allow EPWM3 to enable ADC
EPwm7Regs.ETSEL.bit.SOCAEN = 1;
EPwm7Regs.ETSEL.bit.SOCASEL = 0x1;
EPwm7Regs.ETPS.bit.SOCACNT = 0x0;
EPwm7Regs.ETPS.bit.SOCAPRD = 0x1;
EPwm7Regs.ETSEL.bit.INTEN = 1;
EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Select INT on zero event
EPwm7Regs.ETPS.bit.INTPRD = ET_1ST;
PieCtrlRegs.PIEIER3.bit.INTx7 = 1; //
IER |= M_INT3; // Enable CPU INT
EPwm8Regs.TBCTR = 0;
EPwm8Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm8Regs.TBCTL.bit.CLKDIV = 0;
EPwm8Regs.TBCTL.bit.CTRMODE = 2;
EPwm8Regs.TBCTL.bit.PHSEN = 1;
EPwm8Regs.TBCTL.bit.SYNCOSEL =0;
EPwm8Regs.TBCTL.bit.PRDLD= 0;
EPwm8Regs.AQCTLA.bit.CBD = 2;
EPwm8Regs.AQCTLA.bit.ZRO = 1;
EPwm8Regs.AQCTLB.bit.CAU = 2;
EPwm8Regs.AQCTLB.bit.PRD = 1;
EPwm8Regs.AQSFRC.bit.RLDCSF= 3;
EPwm8Regs.AQCSFRC.bit.CSFA = 1;
EPwm8Regs.AQCSFRC.bit.CSFB = 2;
EPwm8Regs.DBCTL.all = 0;
EPwm8Regs.CMPCTL.bit.SHDWAMODE = 0x0;
EPwm8Regs.CMPCTL.bit.SHDWBMODE = 0x0;
EPwm8Regs.CMPCTL.bit.LOADAMODE = 0x0;
EPwm8Regs.CMPCTL.bit.LOADBMODE = 0x0;
EPwm8Regs.TBPRD = 1169;
EPwm8Regs.TBPRDHR = (151<< 8); //test
EPwm8Regs.CMPA.bit.CMPA = 120;
EPwm8Regs.CMPB.bit.CMPB = 1169- 120;
EPwm8Regs.DBRED = 800;
EPwm8Regs.DBFED = 800;
EPwm8Regs.TBPHS.bit.TBPHS = 0;
EALLOW; //test
#if HR_ENABLED
EPwm8Regs.HRCNFG.bit.EDGMODE = 3;
EPwm8Regs.HRCNFG.bit.CTLMODE = 0;
EPwm8Regs.HRCNFG.bit.HRLOAD = 2;
EPwm8Regs.HRCNFG.bit.SELOUTB = 0;
EPwm8Regs.HRCNFG.bit.AUTOCONV = 1;
EPwm8Regs.HRCNFG.bit.SWAPAB = 0;
EPwm8Regs.HRCNFG.bit.EDGMODEB = 3;
EPwm8Regs.HRCNFG.bit.CTLMODEB = 0;
EPwm8Regs.HRCNFG.bit.HRLOADB = 2;
EPwm8Regs.HRPCTL.bit.HRPE = 1;
EPwm8Regs.TBCTL.bit.SWFSYNC = 1;
#endif
EDIS;
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO14 =0x0;
GpioCtrlRegs.GPAGMUX1.bit.GPIO15 =0x0;
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0x1; // set as EPWM8A
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0x1; // set as EPWM8B
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO1 (EPWM1B)
EDIS;
