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TMS320F28335: When the XINTF latches and read the data

Rayna Wang
Expert 3680 points
Part Number: TMS320F28335

Hi Expert,

Customer finds that the data to read access is latched a XTIMCLK before RD rising edge, but not at the moment of RD rising edge.

They wonder if the mechanism is normal, and how to configure XINTF to latch the value at the moment of RD rising edge?

Attachment is the register configuration of XINTF. Could you please help to review it and answer the questions?

Thanks!

DSP2833x_Xintf.c
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// TI File $Revision: /main/5 $
// Checkin $Date: August 16, 2007 11:06:26 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.c
//
// TITLE: DSP2833x Device External Interface Init & Support Functions.
//
// DESCRIPTION:
//
// Example initialization function for the external interface (XINTF).
// This example configures the XINTF to its default state. For an
// example of how this function being used refer to the
// examples/run_from_xintf project.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitXINTF:
//---------------------------------------------------------------------------
// This function initializes the External Interface the default reset state.
//
// Do not modify the timings of the XINTF while running from the XINTF. Doing
// so can yield unpredictable results
void InitXintf(void)
{
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
// For an example of an XINTF configuration used with the
// F28335 eZdsp, refer to the examples/run_from_xintf project.
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 1;
XintfRegs.XTIMING0.bit.XWRACTIVE = 2;
XintfRegs.XTIMING0.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 2;
XintfRegs.XTIMING0.bit.XRDACTIVE = 4;
XintfRegs.XTIMING0.bit.XRDTRAIL = 2;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Best Regards

Rayna

  • 0
    TI__Guru 62975 points

    Rayna,

    This information is included in the datasheet and XINTF user guide.

    With respect to the XRD behavior, I would consider the latch operation to be completed when the signal is released back to high. The relevant setup time from the datasheet must be satisfied:

    This is consistent with SRAM devices in general:

    -Tommy