TMS320F28027F: Overmodulation difference between Lab10 a and Lab10c

Hi,

I also don't see SVGENCURRENT_RunIgnoreShunt() gets called anywhere, when does this function be used?

Thanks.

The similar function of the SVGENCURRENT_RunIgnoreShunt() is implemented in SVGENCURRENT_compPwmData(). You might change the code as below.

if(measurableShuntThisCycle >= two_phase_measurable)
{
gAdcData.I.value[0] = gIavg.value[0];
gAdcData.I.value[1] = gIavg.value[1];
gAdcData.I.value[2] = gIavg.value[2];
}

Chanigng to this in mainISR():

if(measurableShuntThisCycle >= two_phase_measurable)

No improvement observed.

Reducing the Kp by half stopped the constant current instability, but waveform is not as sinusoidal anymore.

Is it possible the transition between 3phase current sampling and reconstruction attribute to the current loop instability?

No. The main reason should be the feedback currents are not good if they are reconstructed for over-modulation. Are you working on your own board or TI EVM kit? You might use the PWMDAC to check if the feedback current is better for control if you are using the TI EVM kit.

Amy updates? Do you have a chance to check the feedback current using a PWMDAC? Or limit the USER_MAX_VS_MAG_PU to less than (0.575)?

Hi Yanming,

I did not have the chance to check PWMDAC as this is on custom board. I am using 0.55 as the USER_MAX_VS_MAG_PU limit.

I found out when I changed the ADC clock prescaler ADCCTL2.CLKDIV2EN to 0, which makes the ADC clock same as 60MHz, the instability problem is gone.

I would like to check for few things to confirm the ACQPS is set correctly:

1) What is the maximum allowed ADC clock? From 28027 sprs523 datasheet is it 60MHz?

2) In many eval-kit, including DRV8312kit, in hal.c, HAL_OscTempComp() function, CLKDIV2EN is set to 2:

ADC_setDivideSelect(obj->adcHandle,ADC_DivideSelect_ClkIn_by_2);

In HAL_setupAdcs() function, each Soc ACQPS is set to ADC_SocSampleDelay_7_cycles.

The above settings seems to violate the minimum sample window size of 7 ADC clock cycles from sprs523 datasheet.

SYSCLK is 60MHz, CLKDIV2EN is set to 2 so ADCCLK is 30MHz, 7 ADC clock is 233.33ns.

ACQPS is set to 6 (ADC_SocSampleDelay_7_cycles), so sample window is 116.67ns, which is less than 7 ADC clocks.

3) How do I determine the maximum ACQPS can be set?

Thanks,

SY Chan

Hi Yanming,

With the ADC clock 60MHz, now, changing minWidth_microseconds from (2.0) to lower value to avoid current reconstruction (compMode is always "all_phase_measurable"), current waveform is almost sinusoidal.

4) How low I can set the minWidth to? I am using DRV8323S.

5) Does OVM must always pair with current reconstruction? At the current settings, motor is running at Vs=0.52, with compMode always "all_phase_measurable".

Thanks,

SY Chan

Hi Yanming,

2) The source codes for eval-board examples set the SYSCLK=60MHz, ADCCLK=30MHz (ADCCTL2.CLKDIV2EN=1), so 7*ADC cycles is 233.33ns.

ACQPS is set to 6, so sample window is 116.67ns.

Datasheet specified minimum sample window is 7*ADC cycles, 233.33ns, but the sample window set is only 116.67ns.

Is my interpretation correct?

5) After Vs exceeds 0.5, there is an operation area, where all phases are still measurable due to minWidth settings, during this time, current construction is not used. Is my interpretation correct?

While looking up the datasheets, the acquisition windowsor F28337 and F2807x devices is based on SYSCLK, not ADCCLK. I might have wrongly assumed this applies to F2802x devices. Can you confirm my mistake?

In my case, reducing the sample window with higher ADCCLK seems to make the control more stable, do you have any insight of this?

Thank you.

SY