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XINT Question using 2 chips

Christopher Taylor
Intellectual 690 points

I have been given a board with the 28335 DSP and 2 external ram chips.  There is an AND gate on the chip selects and each chip has 16 data lines going to it.  From my understanding of the documentation this would mean a single zone of 1M x 32 bits.  Is this correct?  This is my first project using external RAM and want to make sure that I am understanding the configuration properly.  My plan for the external memory is to use the DSP BIOS memory buffers for comms data.  Any help or suggestions are warmly appreciated.

  • 0
    Expert 2355 points

    I am also just designing my first board with XINTF so I'm not 100% sure but after reading the documentation I would refer you to Figure 5 on Page 15 of SPRU949 (XINTF reference guide).  This shows the connection between a 32-bit bus and the F28335.  If you wire it up as shown you should get a working solution. 

    One thing to be careful with is the CS lines.  These CS are generated by accesses in the F28335 to my understanding.  Since only one address can be accessed at once in the F28335 only one CS line will be low at one time.  One solution would be the following:

    RAMCS = !(!CS6  OR !CS7) = CS6 AND CS7 (as you already have)

    A20 (extra higher order address bus line on the RAM) = !CS7

    This would mean that the RAM would be selected whether you access bank 6 or 7 and when you access bank 7 it will turn on the highest address bit to basically extend your addressing across the the two banks.  Note that each bank gives 1M x 16 bits (512K x 32 bits) so if you carefully combine them together (as above) you will get 1M x 32 bits.

    Tim