TMS320F28377S: EPWM output set to low

dongkwan yoon

Prodigy 170 points

Part Number: TMS320F28377S

Hello

I have a problem that is related to EPWM output from TMS320F28377S.

Two control boards are synchronized to control the circuit.

The master board performs control and sends a duty reference to the slave board using SPI communication.

However, PWM does not occur at one cycle during the PWM operation as shown in the picture.

The PWM port where the above phenomenon occurs has no regularity, and the constant occurs only in the duty section of about 0.5.

ADC interrupt and SPI interrupts are working in Slave Board.

At first, two interrupts were operated, so it was expected that they would collide with each other.

If the power conversion circuit does not operate, it operates normally. So I think the interrupt seems to be fine. and the initialization code seems to be fine too.

I really appreciate it if you could give me any hint or suggestions.

Thank you very much.

over 5 years ago

0 dongkwan yoon over 5 years ago

Prodigy 170 points

Sorry, I forget the picture

C1 is EPWM1A, and C3 is EPWM2A.

Thank you very much.

0 Subrahmanya over 5 years ago

TI__Mastermind 24095 points

Hi,

dongkwan yoon said:
The master board performs control and sends a duty reference to the slave board using SPI communication.

Is the PWM pulse missing at the master or the slave side?

dongkwan yoon said:
However, PWM does not occur at one cycle during the PWM operation as shown in the picture.

Is this happening at the time when you update the duty cycle received over SPI?

dongkwan yoon said:
Two control boards are synchronized to control the circuit.

How is the synchronization done? Is this done using EXTSYNCIN across master and slave devices??

0 dongkwan yoon over 5 years ago in reply to Subrahmanya

Prodigy 170 points

Hi, Thank you for your reply.

1 . PWM pulse missing at only in slave board side.

2. I couldn't confirm it exactly.

SPI interrupt syntax is as follows.

I checked the ChipSelect and GPIO57

I think that the PWM update is in progress after the communication is over because the pulse(Set after Clear) of GPIO57 operate after the ChipSelect signal returns to High.

interrupt void spibRx_int(){

OPMODE = 2;

duty_ref_lim = SpibRegs.SPIRXBUF & 0xffff;

GpioDataRegs.GPBSET.bit.GPIO57 = 1;
GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1;

EPwm1Regs.CMPA.bit.CMPA = (int)(duty_top_phaseB * (float)pwm_g1.phase_duty_max_scaled);
EPwm2Regs.CMPA.bit.CMPA = (int)(duty_bot_phaseB * (float)pwm_g1.phase_duty_max_scaled);
EPwm3Regs.CMPA.bit.CMPA = (int)(duty_top_phaseA * (float)pwm_g1.phase_duty_max_scaled);
EPwm4Regs.CMPA.bit.CMPA = (int)(duty_bot_phaseA * (float)pwm_g1.phase_duty_max_scaled);

SpibRegs.SPIFFRX.bit.RXFFOVFCLR = 1;
SpibRegs.SPIFFRX.bit.RXFFINTCLR = 1;
PieCtrlRegs.PIEACK.all |= M_INT6;
rx_cnt ++;
}

3. Yes, Master Board use OutputXbar as a SYNCOUT, and Slave Board use InputXbar as a SYNCIN.

looking forward for your answer.

Thanks.

0 Subrahmanya over 5 years ago in reply to dongkwan yoon

TI__Mastermind 24095 points

Hi,

dongkwan yoon said:
2. I couldn't confirm it exactly.

Code looks fine. You can check the values being updated are as expected.

dongkwan yoon said:
Yes, Master Board use OutputXbar as a SYNCOUT, and Slave Board use InputXbar as a SYNCIN.

Depending on when the Sync pulse is applied from master to slave, there is a chance that a compare event is missed due to the sudden change in the compare value due to synchronization. you can check if that is the case by disabling synchronization across devices.

0 dongkwan yoon over 5 years ago in reply to Subrahmanya

Prodigy 170 points

Thank you for your kind reply.

Is it possible that the sync signal can be ignored because of noise?

or What does it mean that 'there is a chance that a compare event is missed due to the sudden change in the compare value due to synchronization' ?

The sync signal is periodic, so to me, it is difficult to understand that the comparison value suddenly changes due to synchronization.

If the problem is that the comparison value suddenly changes, could it be related to the SPI interrupt? Or is there a way to check it out?

How can I check if the sync signal is missing?

Since the power conversion circuit cannot be driven without the sync, there is no way to separate and check the sync signal.

Compared to master, Slave module is delayed by 90degrees from the ePWM 1A/1B to ePWM 4A/4B, and from ePWM 5A5B to 6A6B are delayed 0 degrees. Could it be related too?

---- ePWM code set up at slave module ---

---Inputxbar set up---

EALLOW;
GpioCtrlRegs.GPBGMUX1.bit.GPIO34 = 0;
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
GpioCtrlRegs.GPBPUD.bit.GPIO34= 0;
GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3;
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0;

EDIS;

EALLOW;
InputXbarRegs.INPUT5SELECT = 34;
EDIS;

---epwm interrupt set up---

interrupt void epwm1_timer_isr(void)
{
epwm_isr_flag = 1;

EPwm1Regs.TBCTL.bit.SWFSYNC = 0; // MASTER SYNC
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP3;
}

---epwm set up(TBPHS)---

EPwm1Regs.TBPRD = (unsigned int)5000.0;
EPwm1Regs.TBPHS.bit.TBPHS = (unsigned int)2500.0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm1Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

(EPwm 1 ~ EPwm 4 set up are same.)

EPwm5Regs.TBPRD = (unsigned int)5000.0;
EPwm5Regs.TBPHS.bit.TBPHS = (unsigned int)0.0;
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm5Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

(EPwm 5 ~ EPwm 6 set up are same.)

looking forward for your answer.

Thank you very much.

0 Subrahmanya over 5 years ago in reply to dongkwan yoon

TI__Mastermind 24095 points

Hi,

dongkwan yoon said:

Is it possible that the sync signal can be ignored because of noise?

Noise could actually cause some unintended sync pulse on the input.

You can also turn on the GPIO qualification to filter noise. Look for GPIO Qualification logic in the device TRM document.

dongkwan yoon said:
The sync signal is periodic, so to me, it is difficult to understand that the comparison value suddenly changes due to synchronization.

Sync pulse is periodic but the 2 different devices can have different frequency and PWM drift over time - due to minor variations in the oscillator/crystal clocks.

dongkwan yoon said:
How can I check if the sync signal is missing?

If possible, by monitoring the Sync signal and PWM outputs and triggering the oscilloscope based on pulse duration.

dongkwan yoon said:
Compared to master, Slave module is delayed by 90degrees from the ePWM 1A/1B to ePWM 4A/4B, and from ePWM 5A5B to 6A6B are delayed 0 degrees. Could it be related too?

I don't think this is a problem.

0 dongkwan yoon over 5 years ago in reply to Subrahmanya

Prodigy 170 points

Thank you for your fast and kind reply.

1. I already tried both conditions where the QSEL register is 3 and 2, but I got the same result.

So now, The QSEL is set '3'

2. And, as you advised me, I will check the PWM and sync signal at the same time.

3. And I think the oscillator's variations are not problem. Because when the power conversion circuit was not driven, there was no problem at all.

looking forward for your answer.

Thank you very much.

0 dongkwan yoon over 5 years ago in reply to dongkwan yoon

Prodigy 170 points

Thank you for your interest.

I checked sync signal and PWM at same time.

I attached the figure.

Green signal is sync, Blue signal is PWM.

I think, Sync signal looks fine.

If CMPA(duty reference which is received by SPI) was the problem, I think it would have been an unwanted PWM.

But As shown in the Figure, PWM(A channel) is set to low. B channel is set to high. (it looks like duty reference or TBPRD set to ZERO).

I doubt TBPRD is set zero during the synchronization process.

Is there any way to check the PWM update error or Synchronization error?

looking forward for your answer.

Thank you very much.

0 Subrahmanya over 5 years ago in reply to dongkwan yoon

TI__Mastermind 24095 points

Hi,

Synchronization does not change the TBPRD value but it changes the TBCNT value - TBCNT gets loaded with the phase (TBPHS).
So, as i mentioned earlier, it could be a combination of value you are updating in the duty and the sync pulse occurrence.
If the TBCNT jumps over the CMPA/B value used for duty control, there is a possibility of missing the compare edge.
Also, from your waveforms the Sync pulse and the rising edge of PWM look very close. If the rising edge generation is impacted due to sync (missing event as I explained earlier) - PWM could stay low for the entire cycle.

dongkwan yoon said:
Is there any way to check the PWM update error or Synchronization error?

Well, these are not really errors and there is no direct way to monitor other than looking at the scope outputs.
if you disable synchronization and check that there is no issue - then it clearly points to the issue of missing event.