CCS/TMS320F28379D: Break Point is not working in software.

Katuri,

Regarding breakpoints: Please see this FAQ post - https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/780932?-FAQ-F05-Why-can-t-I-set-more-than-2-breakpoints-in-flash-

Regarding the break at address:  Please see below and see if they help:

1. https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/788743

2. https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/780656

Thanks and regards,

Vamsi

Hi Vamsi,

 I am  loading software in to flash memory for both CPU-01 and CPU-02.In addition, I am also using section copy from Flash to RAM for both CPU's.I have gone through specified links.However,still i am not sure in the following areas.They are mentioned below.

1.why i am getting message as "Break at address "0x3fec52" with no debug information available, or outside of program code"?please,provide some details related to this.On which case this message will come.is there any issue in my software.Because my programs on respective cpu are executing 

2.while i am using only one CPU(Either CPU-01 or CPU-02),break points are working.But while iam using IPC between two CPU's,break point feature is not working

3.After loading program via debugger in to cpu-01 and cpu-02, i tried to reset and run the both cpu's.Only CPU-01 is executing.i am using boot to flash for both cpu's.Shall i have to send any boot command from CPU-01 to CPU-02? I have seen the following code in ipc example project.But i didn't get the information related to "_STANDALONE","_FLASH".Shall i have to declare these in predefined symbols in build settings?

#ifdef _STANDALONE
#ifdef _FLASH
//
// Send boot command to allow the CPU2 application to begin execution
//
IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
#else
//
// Send boot command to allow the CPU2 application to begin execution
//
IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM);
#endif
#endif

Thanks and Regards

K.Gudaru Venkaiah

Hi Vamsi,

I am using flash to Ram secion copy.I am using break points in my Timer-0 isr code only not before the main function.As per you suggestion,i have to use IPC synchronisation between CPU-01 and CPU-02.

1.I am calling the following function call " IpcSync(IPC_FLAG4); " in while(1) of both CPU's software.After this also break points are not working in my timer-0 isr.Is it ok to call here or i have to call in any ISR?

void IpcSync(Uint16 flag)
{
SendIpcFlag(flag);
WaitForIpcFlag(flag);
AckIpcFlag(flag);
WaitForIpcAck(flag);
}

2.I have not written anything related to waiting of CPU-02(in CPU-02 Software) before the CPU-01 completes the execution of system initialisation.I am just sending the IPCBootCPU2 command in CPU-01  after CPU-01 system,peripheral registers configuration execution.Is it sufficient or do i need to add anything else in the CPU-02 software for waiting purpose?Please,suggest me.

 IPCBootCPU2 command:  IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah,

Regarding breakpoints: Please confirm whether you inserted breakpoints after executing section copy or before.  It does not matter where the breakpoints are. What matters is when you inserted the breakpoints. Please confirm.

I will ask our boot expert to help you further.

Thanks and regards,
Vamsi   

Venkaiah,

You need to call the IPCsync on both cores if you want them sync. If you need to emulate standalone with the debugger, the procedure is:

In order to emulate standalone with debugger connected, the following steps should perform how you expect:

(With each CPU flash programmed already)

1. Reset CPU1 (CPU reset, not restart)

2. Set EMUBOOT to flash CPU1

3. Reset(CPU reset, not restart) CPU2

4. Run CPU2 (Don't set bootmode to flash, for this type of scenario don't use the gel scripts, you want it to go to wait boot)

5. Run CPU1

6. CPU1 will then boot to flash, while CPU2 is waiting for BOOT IPC command

7. CPU1 app will send IPC to boot CPU2 to flash

8. CPU2 will boot to flash and run

If your question regarding boot isn't this, please clarify. 

Best regards

Chris

Hi Chris,

  Thank for your Support.

Regarding IPC Synchronisation:

1.i am calling the function " IpcSync(IPC_FLAG4);"  in while(1) of both CPU's.I mentioned the program outline below.Is it ok or do i need to inlcude more?

Program Outline:

void main(void)

{

     InitSysCtrl(); 

    InitGpio();

    InitPieCtrl();

    -->remiaing initializations

      while(1)

     {

          IpcSync(IPC_FLAG4);

     }

}

void IpcSync(Uint16 flag)
{
SendIpcFlag(flag);
WaitForIpcFlag(flag);
AckIpcFlag(flag);
WaitForIpcAck(flag);
}

Booting Related:

1.I loaded the software in CPU-01 via CCS with emulator.After that I loaded the CPU-02 Software via CCS with emulator only.

2.I Reset the CPU-01 Software.However,i don't know how to "Set EMUBOOT to flash in CPU1" within the CCS.Please,suggest me the way to do.

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah,

Regarding the IpcSync(), that should be fine. They will continue to sync. Not that is matters much, but I'd say the typical use would be to have the IpcSync before each core's main loop and then go into main loop for their actions, etc. I don't see this causing any issues though.

When debugger is connected, CPU1 boot follows the emulation boot flow and boot mode decode. For flash boot, you set 0x0B5A to address 0xD00. You can read more on this in the "Configuring Emulation Boot Options" section of the boot chapter in the device technical reference manual.

Best regards

Chris

Hi Chris,

Regarding IPC Synchronization:

Will you guide me how to synchronize CPU-01 and CPU-02 before entering respective "main" function? To Synchronize CPU-01 and CPU-02 before entering respective "main" function,where  i have to call  IpcSync().Please,suggest me the proper way to synchronize both cpu-01 and cpu-02 before entering respective main function.

Regarding Booting:

I have gone through Configuring Emulation Boot Options.I able to see memory location 0xD00 via  CCS-->View-->Memory Browser.I searched the 0xD00 location and i found 035A in that location.i changed 0xD00 location value from 035A to 0B5A.Is this procedure you are suggesting?.if it is the correct procedure,every time while loading program in to cpu-01,shall i have to write 0x0B5A to 0xD00 location?

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah,

Regarding the IPC Synchronization, you're using the correct API. Essentially on each core what I'm saying is to do the following:

IpcSync(IPC_FLAG0); // or whatever flag you want to use

// By this point, both CPUs are now in sync to start their main loop

while(1)

{

// CPU actions

}

Regarding booting, yes change that 0xD00 location to 0B5A. Once you connect and change the value, you don't have to change it again as long as you're connected with the debugger. The boot flow will overwrite that value if it runs without the debugger so you can see what boot value is being decoded.

Best regards

Chris

Hi Chris,

Regarding IPC synchronization:

 Regarding IPC synchronization, i called the function "IpcSync(IPC_FLAG4);" before entering while(1) on CPU-01 and CPU-02.However,how to check whether both CPU's are Synchronized or not? what parameters i need to look at cpu-01 and cpu-02 to know both CPU's are synchronized or not.I mentioned my idea below to check the CPU-01 and CPU-02 synchronization.Please,tell me this is ok or not.Please,suggest me any better way of testing CPU-01 and CPU-02 Synchronisation.

What i am thinking:

   1.CreateTimer0-isr in both cpu-01 and cpu-02 with same isr time.for example,Timer0-isr will come for every 50e-6 sec in CPU-01 and CPU-02.

   2.Toggle a GPIO(Separate GPIO for CPU-01 and CPU-02) in Timer-0 isr as first instruction in both CPU's.

   3.See the GPIO waveforms in Oscilloscope.if both GPIO's are changing their state at the same instance,then we can say that both CPU's are synchonized. 

Regarding  booting:

I changed the 0xD00 location to 0B5A every time after loading new software.Booting is working fine.However,break points are not working.I am inserting break points in timer-0 isr after software is executing.The break point inserting sequence is mentioned below.

Sequence:

1.Loading the software in CPU-01 and then in CPU-02.

2.Reset the CPU-01 software.Then change the 0xD00 location to 0B5A

3.Reset the CPU-02 software.RUN the cpu-02 software.After RUN,CPU-02 is not running ,it is showing some software break point in debugger.

4.RUN the CPU-01 Software.After that RUN the CPU-02 software.At this point both cpu's are executing software.

5.Now, i am inserting break point in timer-0 isr in CPU-01 or CPU-02.Software execution is not stopping.

Please,suggest me what i need to do?

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah,

Yes, I agree, that seems like a valid way to determine that they are in sync.

Ok, so you've confirmed that CPU2 application is actually reached and executing?

Your breakpoint sequence looks to be fine. Are you right-clicking and inserting a "hardware breakpoint"? This is required for breakpoints when running from flash. Do you have any breakpoint issues when running from RAM?

Best regards

Chris

Hi Chris,

Regarding IPC synchronization:

I have tested the IPC synchronization between cpu-01 and cpu-02 by calling "IpcSync(IPC_FLAG4);"before entering while(1) in both cpu's.I have used two gpio's in timer-0 isr of both CPU's.I toggled GPIO-125 in CPU-01,Timer0 isr.In addition,I toggled GPIO-124 in CPU-02,Timer0 isr.Both timer0 isr's time is 50e-6.However,both the GPIO's states are not changing at the same time.But,there is some overlpping time is available between them.You can see the below image.This is same if i call the "IpcSync(IPC_FLAG4)" function before while(1),or in while(1).Is this ok?please,provide your comments.

Channel details:

Channel-1:CPU-01-GPIO125-Timer0-Isr(Yellow Colour)

Channel-2:CPU-02-GPIO124-Timer0-Isr(light blue Colour)

Regarding Break Points:

I am not executing the software from flash.i am loading the software in flash for both the CPU's.in addition,i used the section copy from flash to RAM.Iam inserting the break points by double clicking the mouse leftside before the instruction(near the line number).While i am using only CPU-01,Break point feature is working,but in case of both cpu's usage,break point feature is not working.

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah

There is an issue and I am unable to view your attached image. If you are seeing them relatively execute at the same time, then all is working. The IpcSync is to have both CPUs start in sync but they won't necessarily stay 100% in sync with each other.

Can you try right-clicking where you typically double click and select breakpoint->hardware breakpoint?

Best regards

Chris

Hi Chris,

Regarding Breakpoint:

  I tired the way you suggested to insert break point.However,it is not working.Software execution is not stopping.

Regarding IPC Synchronization:

Relativey,CPU-01 and CPU-02 Timer0-Isr's GPIO events are coming at same time.However,both GPIO events are not changing at the same instant.Again i attached Oscilloscope image below.

Channel-1:CPU-01 Timer 0-Isr GPIO Toggling

Channel-2:CPU-02 Timer 0-Isr GPIO Toggling

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah,

E2E still seems to be having trouble with the image. Could you try zipping up the image and attaching the zip? When I look a the image, then I'll have a better idea of you're seeing.

Regarding the breakpoint, what version of CCS are you using? You are using the CODE_SECTION pragma to copy your timer ISR to RAM from Flash, is this correct? I've tested this method and the breakpoint was successful in working in the timer ISR when copied from flash to ram on CPU2. I'm using CCS 9.3.0.00012

Best regards

Chris

Hi Chris,

Sections Copy:

I followed the procedure mentioned in the document with title"Copying Compiler Sections From Flash to RAM on the TMS320F28xxx DSCs(SPRAAU8A)".I am copying entire software from flash to RAM not a single ISR.I am using CCS V10.00.I will also check in CCS V9.3 in one or two days?i will update you the result.But as of now break point feature is not working.

IPC Synchronization:

I attached agian the IPC Synchronization test result image in .rar format.

Channel-1:CPU-01 Timer0 Isr GPIO Status

Channel-2:CPU-02 Timer0 Isr GPIO Status

dso_07_28_11_14_21.rar

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah,

On the sections copy, I've updated my example to use that method and I am able to set a breakpoint without issue. Additionally, I installed CCS 10.1 and it also worked there as well. Is it possible to RAR the project so I can take a look? Or at least the linker command files? Is there anything to the example or just setup+timer ISR?

On the IPC Sync, could you update your flow to call the IPCSync then enable the timer and then enter the while loop? If it is possible for the GPIOs to be set closer, maybe their timer freq are off since they are enabled before the SYNC.

Best regards

Chris

Hi Chris,

Break Point:

how to find your method of section copy? from where i can get.I have attached linker command files of both cpu-01 and cpu-02 in .rar format.In addition i,will make a new project with only timer0 isr in both cpu-01 and cpu-02 and i will test related to break point.

IPC Synchronization:

i enable the timer0(CpuTimer0Regs.TCR.bit.TSS=0;) after calling the  IpcSync(IPC_FLAG4) before entering while(1).However,frequent reset happening in cpu-01 and cpu-02 while executing via CCS and debugger. if i run without debugger mode,then both cpu-01 and cpu-02 are executing fine and IPC synchronizing is happening at same instant.Both gpio's toggled in Timer-0 isr of both cpu's changing their states at the same instant.but there is a issue while running in debugging mode via ccs.i attached the image in .rar format related to the IPC Synchronization in standalone mode.

Channel-1:CPU-01 Timer0 isr GPIO toggled

Channel-2:CPU-02 Timer0 isr GPIO toggled

IPC_Synchronize.rar

Thanks and Regards

K.Gudaru Venkaiah

Venkaiah,

E2E for some reason won't let me download the RAR with linkers, seems like link is broken. I followed the document you referenced for the section copy. Essentonally, I took the dual core blinky example from C2000Ware (added timer ISR), added the section copy ASM, edited the codestartbranch.asm with jump to section copy, and edited the linker command files to include copy from flash to ram for all the section copy sections. I referenced the examples that come with that document you linked.

Good to see the IPC sync is better. I don't see this directly affecting the device to reset. You can check the sysctl reset cause register to see if that gives you insight into why it is resetting. If you have other code, may want to check that as well. Make sure you have enough stack, etc.

Best regards

Chris