Other Parts Discussed in Thread: C2000WARE
Hello,
I'm trying monitor my ADC reading of my software at the Watch Window at the right upside corner of the CCS.
Although I apply a DC stable voltage to ADC Input, the reading of ADC that is seen at the window has some much variation. My ADC configuration is as below. How can I solve it?
I tried to configured Epwm3 for soc and it checks ADC result at a frequency of 5kHz, if my code is correct?.
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// Function Protoypes
//
void ConfigureADCa3(void);
void ConfigureEPWMb3(void);
void SetupADCEpwma3(void);
interrupt void adcb3_isr(void);
//
//=====================================
// ADCINA3-Vout Variables
//
float Vout_real=0, Vout_ADC=0;
// Configure the ADC and power it up
ConfigureADCa3();
// Configure the ePWM
ConfigureEPWMb3();
// Setup the ADC for ePWM3 triggered conversions on channel 0
SetupADCEpwma3();
void ConfigureADCa3(void)
{
EALLOW;
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; // Set ADCCLK divider to /4
AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; // 12-bit resolution
AdcaRegs.ADCCTL2.bit.SIGNALMODE = 0; // Single-ended channel conversions (12-bit mode only)
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Set pulse positions to late
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC A
DELAY_US(1000); // Delay for 1ms to allow ADC time to power up
EDIS;
}
void ConfigureEPWMb3(void)
{
EALLOW;
// Assumes ePWM clock is already enabled
EPwm3Regs.TBCTL.bit.CTRMODE = 0; // Freeze counter
EPwm3Regs.TBPRD = 20000; // Set period to 20000 counts (5kHz ??)
EPwm3Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm3Regs.TBPHS.bit.TBPHS = phaseOffset3; // Phase
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // TBCLK pre-scaler = /1
EPwm3Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = 2; // Select SOCA on period match
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA
EPwm3Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// Below codes creates ISR for CNTL_ISR where duty at 0.1 FOR 5kHz
EPwm3Regs.CMPB.bit.CMPB= 1000; // ISR trigger point
EPwm3Regs.ETSEL.bit.INTSEL = 0x6; // INT on CompareB-Up event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = 0x1; // Generate INT on every 1st event
EDIS;
void SetupADCEpwma3(void)
{
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 3; // SOC0 will convert pin A3 for ADC A
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; // Sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 9; // Trigger on ePWM3 SOCA (ePWM3A will trigger)
AdcaRegs.ADCINTSEL3N4.bit.INT3SEL = 0; // End of SOC0 will set INT3 flag for ADC A
//ADCINT3 EOC Source Select, if 0h EOC0 is trigger for ADCINT3
AdcaRegs.ADCINTSEL3N4.bit.INT3E = 1; // Enable INT3 flag
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0x0F; /* SOC0 has HIGHEST Priority*/
EDIS;
}
interrupt void adca3_isr(void) /**** OUTPUT VOLTAGE ADC ISR ****/
{
/* Buck_Vout_ADC shows real voltage at ADC Input */
Vout_ADC = ( ((float) AdcaResultRegs.ADCRESULT0 / 4096) * 3.3 );
/* Buck_Vout_real shows real Iavg value like 2A */
Vout_real = ((Vout_ADC * 16.3) / 3.3);
if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT3)
{
AdcaRegs.ADCINTOVFCLR.bit.ADCINT3 = 1; //clear INT1 overflow flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT3 = 1; //clear INT1 flag
}
// Return from interrupt
AdcaRegs.ADCINTFLGCLR.bit.ADCINT3 = 1; // Clear ADC INT3 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; // Acknowledge PIE group 10 to enable further interrupts
}