CM Ethernet issue (lwip)

521177 14
R PC 0x0000000B 0x00210FCC
R SP 0x0000000B 0x1FFFD030
R LR 0x0000000B 0x00210FD1
R xPSR 0x0000000B 0x61000000
R R0 0x0000000B 0x00000258
R R1 0x0000000B 0x00000000
R R2 0x0000000B 0x00000000
R R3 0x0000000B 0x20008EF4
R R4 0x0000000B 0x00000000
R R5 0x0000000B 0x20011290
R R6 0x0000000B 0x0000D23C
R R7 0x0000000B 0x400FD000
R R8 0x0000000B 0x20011288
R R9 0x0000000B 0x200112A0
R R10 0x0000000B 0x2001129E
R R11 0x0000000B 0x20011286
R R12 0x0000000B 0x3000046A
R R13 0x0000000B 0x1FFFD030
R R14 0x0000000B 0x00210FD1
R MSP 0x0000000B 0x1FFFD030
R PSP 0x0000000B 0x00000000
R DSP 0x0000000B 0x00000000
R CTRL_FAULT_BASE_PRI 0x0000000B 0x00000000
R AES_AES_KEY2_6 0x0000000B 0x00000000
R AES_AES_KEY2_7 0x0000000B 0x00000000
R AES_AES_KEY2_4 0x0000000B 0x00000000
R AES_AES_KEY2_5 0x0000000B 0x00000000
R AES_AES_KEY2_2 0x0000000B 0x00000000
R AES_AES_KEY2_3 0x0000000B 0x00000000
R AES_AES_KEY2_0 0x0000000B 0x00000000
R AES_AES_KEY2_1 0x0000000B 0x00000000
R AES_AES_KEY1_6 0x0000000B 0x00000000
R AES_AES_KEY1_7 0x0000000B 0x00000000
R AES_AES_KEY1_4 0x0000000B 0x00000000
R AES_AES_KEY1_5 0x0000000B 0x00000000
R AES_AES_KEY1_2 0x0000000B 0x00000000
R AES_AES_KEY1_3 0x0000000B 0x00000000
R AES_AES_KEY1_0 0x0000000B 0x00000000
R AES_AES_KEY1_1 0x0000000B 0x00000000
R AES_AES_IV_IN_OUT_0 0x0000000B 0x00000000
R AES_AES_IV_IN_OUT_1 0x0000000B 0x00000000
R AES_AES_IV_IN_OUT_2 0x0000000B 0x00000000
R AES_AES_IV_IN_OUT_3 0x0000000B 0x00000000
R AES_AES_CTRL 0x0000000B 0x80000000
R AES_AES_C_LENGTH_0 0x0000000B 0x00000000
R AES_AES_C_LENGTH_1 0x0000000B 0x00000000
R AES_AES_AUTH_LENGTH 0x0000000B 0x00000000
R AES_AES_DATA_IN_OUT_0 0x0000000B 0x00000000
R AES_AES_DATA_IN_OUT_1 0x0000000B 0x00000000
R AES_AES_DATA_IN_OUT_2 0x0000000B 0x00000000
R AES_AES_DATA_IN_OUT_3 0x0000000B 0x00000000
R AES_AES_TAG_OUT_0 0x0000000B 0x00000000
R AES_AES_TAG_OUT_1 0x0000000B 0x00000000
R AES_AES_TAG_OUT_2 0x0000000B 0x00000000
R AES_AES_TAG_OUT_3 0x0000000B 0x00000000
R AES_AES_REV 0x0000000B 0x40000B02
R AES_AES_SYSCONFIG 0x0000000B 0x00000001
R AES_AES_SYSSTATUS 0x0000000B 0x00000001
R AES_AES_IRQSTATUS 0x0000000B 0x00000000
R AES_AES_IRQENABLE 0x0000000B 0x00000000
R AES_AES_DIRTY_BITS 0x0000000B 0x00000001
R AES_SS_AESDMAINTEN 0x0000000B 0x00000000
R AES_SS_AESDMASTATUS 0x0000000B 0x00000000
R AES_SS_AESDMASTATUSCLR 0x0000000B 0x00000000
R CANA_CAN_CTL 0x0000000B 0x00000000
R CANA_CAN_ES 0x0000000B 0x00000000
R CANA_CAN_ERRC 0x0000000B 0x00000000
R CANA_CAN_BTR 0x0000000B 0x00000000
R CANA_CAN_INT 0x0000000B 0x00000000
R CANA_CAN_TEST 0x0000000B 0x00000000
R CANA_CAN_PERR 0x0000000B 0x00000000
R CANA_CAN_RAM_INIT 0x0000000B 0x00000000
R CANA_CAN_GLB_INT_EN 0x0000000B 0x00000000
R CANA_CAN_GLB_INT_FLG 0x0000000B 0x00000000
R CANA_CAN_GLB_INT_CLR 0x0000000B 0x00000000
R CANA_CAN_ABOTR 0x0000000B 0x00000000
R CANA_CAN_TXRQ_X 0x0000000B 0x00000000
R CANA_CAN_TXRQ_21 0x0000000B 0x00000000
R CANA_CAN_NDAT_X 0x0000000B 0x00000000
R CANA_CAN_NDAT_21 0x0000000B 0x00000000
R CANA_CAN_IPEN_X 0x0000000B 0x00000000
R CANA_CAN_IPEN_21 0x0000000B 0x00000000
R CANA_CAN_MVAL_X 0x0000000B 0x00000000
R CANA_CAN_MVAL_21 0x0000000B 0x00000000
R CANA_CAN_IP_MUX21 0x0000000B 0x00000000
R CANA_CAN_IF1CMD 0x0000000B 0x00000000
R CANA_CAN_IF1MSK 0x0000000B 0x00000000
R CANA_CAN_IF1ARB 0x0000000B 0x00000000
R CANA_CAN_IF1MCTL 0x0000000B 0x00000000
R CANA_CAN_IF1DATA 0x0000000B 0x00000000
R CANA_CAN_IF1DATB 0x0000000B 0x00000000
R CANA_CAN_IF2CMD 0x0000000B 0x00000000
R CANA_CAN_IF2MSK 0x0000000B 0x00000000
R CANA_CAN_IF2ARB 0x0000000B 0x00000000
R CANA_CAN_IF2MCTL 0x0000000B 0x00000000
R CANA_CAN_IF2DATA 0x0000000B 0x00000000
R CANA_CAN_IF2DATB 0x0000000B 0x00000000
R CANA_CAN_IF3OBS 0x0000000B 0x00000000
R CANA_CAN_IF3MSK 0x0000000B 0x00000000
R CANA_CAN_IF3ARB 0x0000000B 0x00000000
R CANA_CAN_IF3MCTL 0x0000000B 0x00000000
R CANA_CAN_IF3DATA 0x0000000B 0x00000000
R CANA_CAN_IF3DATB 0x0000000B 0x00000000
R CANA_CAN_IF3UPD 0x0000000B 0x00000000
R CANB_CAN_CTL 0x0000000B 0x00000000
R CANB_CAN_ES 0x0000000B 0x00000000
R CANB_CAN_ERRC 0x0000000B 0x00000000
R CANB_CAN_BTR 0x0000000B 0x00000000
R CANB_CAN_INT 0x0000000B 0x00000000
R CANB_CAN_TEST 0x0000000B 0x00000000
R CANB_CAN_PERR 0x0000000B 0x00000000
R CANB_CAN_RAM_INIT 0x0000000B 0x00000000
R CANB_CAN_GLB_INT_EN 0x0000000B 0x00000000
R CANB_CAN_GLB_INT_FLG 0x0000000B 0x00000000
R CANB_CAN_GLB_INT_CLR 0x0000000B 0x00000000
R CANB_CAN_ABOTR 0x0000000B 0x00000000
R CANB_CAN_TXRQ_X 0x0000000B 0x00000000
R CANB_CAN_TXRQ_21 0x0000000B 0x00000000
R CANB_CAN_NDAT_X 0x0000000B 0x00000000
R CANB_CAN_NDAT_21 0x0000000B 0x00000000
R CANB_CAN_IPEN_X 0x0000000B 0x00000000
R CANB_CAN_IPEN_21 0x0000000B 0x00000000
R CANB_CAN_MVAL_X 0x0000000B 0x00000000
R CANB_CAN_MVAL_21 0x0000000B 0x00000000
R CANB_CAN_IP_MUX21 0x0000000B 0x00000000
R CANB_CAN_IF1CMD 0x0000000B 0x00000000
R CANB_CAN_IF1MSK 0x0000000B 0x00000000
R CANB_CAN_IF1ARB 0x0000000B 0x00000000
R CANB_CAN_IF1MCTL 0x0000000B 0x00000000
R CANB_CAN_IF1DATA 0x0000000B 0x00000000
R CANB_CAN_IF1DATB 0x0000000B 0x00000000
R CANB_CAN_IF2CMD 0x0000000B 0x00000000
R CANB_CAN_IF2MSK 0x0000000B 0x00000000
R CANB_CAN_IF2ARB 0x0000000B 0x00000000
R CANB_CAN_IF2MCTL 0x0000000B 0x00000000
R CANB_CAN_IF2DATA 0x0000000B 0x00000000
R CANB_CAN_IF2DATB 0x0000000B 0x00000000
R CANB_CAN_IF3OBS 0x0000000B 0x00000000
R CANB_CAN_IF3MSK 0x0000000B 0x00000000
R CANB_CAN_IF3ARB 0x0000000B 0x00000000
R CANB_CAN_IF3MCTL 0x0000000B 0x00000000
R CANB_CAN_IF3DATA 0x0000000B 0x00000000
R CANB_CAN_IF3DATB 0x0000000B 0x00000000
R CANB_CAN_IF3UPD 0x0000000B 0x00000000
R ERRORLOG_UCERRFLG 0x0000000B 0x00000000
R ERRORLOG_UCERRSET 0x0000000B 0x00000000
R ERRORLOG_UCERRCLR 0x0000000B 0x00000000
R ERRORLOG_UCM4EADDR 0x0000000B 0x00000000
R ERRORLOG_UCEMACEADDR 0x0000000B 0x00000000
R ERRORLOG_UCuDMAEADDR 0x0000000B 0x00000000
R ERRORLOG_UCEtherCATMEMREADDR 0x0000000B 0x00000000
R ERRORLOG_UCEMACMEMREADDR 0x0000000B 0x00000000
R ERRORLOG_BUSFAULTFLG 0x0000000B 0x00000000
R ERRORLOG_BUSFAULTCLR 0x0000000B 0x00000000
R ERRORLOG_M4BUSFAULTADDR 0x0000000B 0x00000000
R ERRORLOG_uDMABUSFAULTADDR 0x0000000B 0x00000000
R ERRORLOG_EMACBUSFAULTADDR 0x0000000B 0x00000000
R ERRORLOG_CERRFLG 0x0000000B 0x00000000
R ERRORLOG_CERRSET 0x0000000B 0x00000000
R ERRORLOG_CERRCLR 0x0000000B 0x00000000
R ERRORLOG_CM4EADDR 0x0000000B 0x00000000
R ERRORLOG_CEMACEADDR 0x0000000B 0x00000000
R ERRORLOG_CuDMAEADDR 0x0000000B 0x00000000
R ERRORLOG_CERRCNT 0x0000000B 0x00000000
R ERRORLOG_CERRTHRES 0x0000000B 0x00000000
R ERRORLOG_CEINTFLG 0x0000000B 0x00000000
R ERRORLOG_CEINTSET 0x0000000B 0x00000000
R ERRORLOG_CEINTCLR 0x0000000B 0x00000000
R ERRORLOG_CEINTEN 0x0000000B 0x00000000
R DcsmCommonRegs_FLSEM 0x0000000B 0x00000000
R DcsmCommonRegs_SECTSTAT1 0x0000000B 0x0FFFFFFF
R DcsmCommonRegs_SECTSTAT2 0x0000000B 0x0FFFFFFF
R DcsmCommonRegs_SECTSTAT3 0x0000000B 0x0FFFFFFF
R DcsmCommonRegs_RAMSTAT1 0x0000000B 0x000FFFFF
R DcsmCommonRegs_RAMSTAT2 0x0000000B 0xFFFFFF0F
R DcsmCommonRegs_RAMSTAT3 0x0000000B 0x000FFFFF
R DcsmCommonRegs_SECERRSTAT 0x0000000B 0x00000000
R DcsmCommonRegs_SECERRCLR 0x0000000B 0x00000000
R DcsmCommonRegs_SECERRFRC 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_LINKPOINTER 0x0000000B 0xFFFFFFFF
R DcsmZ1Regs_Z1_OTPSECLOCK 0x0000000B 0x00000FF0
R DcsmZ1Regs_Z1_JLM_ENABLE 0x0000000B 0x0000000F
R DcsmZ1Regs_Z1_LINKPOINTERERR 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_GPREG1 0x0000000B 0xFFFFFFFF
R DcsmZ1Regs_Z1_GPREG2 0x0000000B 0xFFFFFFFF
R DcsmZ1Regs_Z1_GPREG3 0x0000000B 0xFFFFFFFF
R DcsmZ1Regs_Z1_GPREG4 0x0000000B 0xFFFFFFFF
R DcsmZ1Regs_Z1_CSMKEY0 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CSMKEY1 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CSMKEY2 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CSMKEY3 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CR 0x0000000B 0x0060000F
R DcsmZ1Regs_Z1_GRABSECT1R 0x0000000B 0x0FFFFFFF
R DcsmZ1Regs_Z1_GRABSECT2R 0x0000000B 0x0FFFFFFF
R DcsmZ1Regs_Z1_GRABSECT3R 0x0000000B 0x0FFFFFFF
R DcsmZ1Regs_Z1_GRABRAM1R 0x0000000B 0x000FFFFF
R DcsmZ1Regs_Z1_GRABRAM2R 0x0000000B 0xFFFFFF0F
R DcsmZ1Regs_Z1_GRABRAM3R 0x0000000B 0x000FFFFF
R DcsmZ1Regs_Z1_EXEONLYSECT1R 0x0000000B 0x3FFF3FFF
R DcsmZ1Regs_Z1_EXEONLYSECT2R 0x0000000B 0x00003FFF
R DcsmZ1Regs_Z1_EXEONLYRAM1R 0x0000000B 0xFFC303FF
R DcsmZ1Regs_Z1_JTAGKEY0 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_JTAGKEY1 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_JTAGKEY2 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_JTAGKEY3 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CMACKEY0 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CMACKEY1 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CMACKEY2 0x0000000B 0x00000000
R DcsmZ1Regs_Z1_CMACKEY3 0x0000000B 0x00000000
R DcsmZ2Regs_Z2_LINKPOINTER 0x0000000B 0xFFFFFFFF
R DcsmZ2Regs_Z2_OTPSECLOCK 0x0000000B 0x00000FF0
R DcsmZ2Regs_Z2_LINKPOINTERERR 0x0000000B 0x00000000
R DcsmZ2Regs_Z2_GPREG1 0x0000000B 0xFFFFFFFF
R DcsmZ2Regs_Z2_GPREG2 0x0000000B 0xFFFFFFFF
R DcsmZ2Regs_Z2_GPREG3 0x0000000B 0xFFFFFFFF
R DcsmZ2Regs_Z2_GPREG4 0x0000000B 0xFFFFFFFF
R DcsmZ2Regs_Z2_CSMKEY0 0x0000000B 0x00000000
R DcsmZ2Regs_Z2_CSMKEY1 0x0000000B 0x00000000
R DcsmZ2Regs_Z2_CSMKEY2 0x0000000B 0x00000000
R DcsmZ2Regs_Z2_CSMKEY3 0x0000000B 0x00000000
R DcsmZ2Regs_Z2_CR 0x0000000B 0x0060000F
R DcsmZ2Regs_Z2_GRABSECT1R 0x0000000B 0x0FFFFFFF
R DcsmZ2Regs_Z2_GRABSECT2R 0x0000000B 0x0FFFFFFF
R DcsmZ2Regs_Z2_GRABSECT3R 0x0000000B 0x0FFFFFFF
R DcsmZ2Regs_Z2_GRABRAM1R 0x0000000B 0x000FFFFF
R DcsmZ2Regs_Z2_GRABRAM2R 0x0000000B 0xFFFFFF0F
R DcsmZ2Regs_Z2_GRABRAM3R 0x0000000B 0x000FFFFF
R DcsmZ2Regs_Z2_EXEONLYSECT1R 0x0000000B 0x3FFF3FFF
R DcsmZ2Regs_Z2_EXEONLYSECT2R 0x0000000B 0x00003FFF
R DcsmZ2Regs_Z2_EXEONLYRAM1R 0x0000000B 0xFFC303FF
R DIAGERRORLOG_DIAGERRFLG 0x0000000B 0x00000000
R DIAGERRORLOG_DIAGERRCLR 0x0000000B 0x00000000
R DIAGERRORLOG_DIAGERRADDR 0x0000000B 0x00000000
R CSFR_MMSR 0x0000000D 0x00
R CSFR_BFSR 0x0000000D 0x00
R CSFR_UFSR 0x0000000F 0x0000
R ESCSS_ESCSS_IPREVNUM 0x0000000B 0x00000000
R ESCSS_ESCSS_INTR_RIS 0x0000000B 0x00000000
R ESCSS_ESCSS_INTR_MASK 0x0000000B 0x00000000
R ESCSS_ESCSS_INTR_MIS 0x0000000B 0x00000000
R ESCSS_ESCSS_INTR_CLR 0x0000000B 0x00000000
R ESCSS_ESCSS_INTR_SET 0x0000000B 0x00000000
R ESCSS_ESCSS_LATCH_SEL 0x0000000B 0x00000000
R ESCSS_ESCSS_ACCESS_CTRL 0x0000000B 0x00000000
R ESCSS_ESCSS_GPIN_DAT 0x0000000B 0x00000000
R ESCSS_ESCSS_GPIN_PIPE 0x0000000B 0x00000000
R ESCSS_ESCSS_GPIN_GRP_CAP_SEL 0x0000000B 0x00000000
R ESCSS_ESCSS_GPOUT_DAT 0x0000000B 0x00000000
R ESCSS_ESCSS_GPOUT_PIPE 0x0000000B 0x00000000
R ESCSS_ESCSS_GPOUT_GRP_CAP_SEL 0x0000000B 0x00000000
R ESCSS_ESCSS_MEM_TEST 0x0000000B 0x00000000
R ESCSS_ESCSS_RESET_DEST_CONFIG 0x0000000B 0x00000000
R ESCSS_ESCSS_SYNC0_CONFIG 0x0000000B 0x00000000
R ESCSS_ESCSS_SYNC1_CONFIG 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_CONFIG_LOCK 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_MISC_IO_CONFIG 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_PHY_IO_CONFIG 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_SYNC_IO_CONFIG 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_LATCH_IO_CONFIG 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_GPIN_SEL 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_GPIN_IOPAD_SEL 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_GPOUT_SEL 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_GPOUT_IOPAD_SEL 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_LED_CONFIG 0x0000000B 0x00000000
R ESCSSCONFIG_ESCSS_MISC_CONFIG 0x0000000B 0x00000000
R ETHERNET_MAC_Configuration 0x0000000B 0x0000A003
R ETHERNET_MAC_Ext_Configuration 0x0000000B 0x00000000
R ETHERNET_MAC_Packet_Filter 0x0000000B 0x00000000
R ETHERNET_MAC_Watchdog_Timeout 0x0000000B 0x00000000
R ETHERNET_MAC_Hash_Table_Reg0 0x0000000B 0x00000000
R ETHERNET_MAC_Hash_Table_Reg1 0x0000000B 0x00000000
R ETHERNET_MAC_VLAN_Tag_Ctrl 0x0000000B 0x00000000
R ETHERNET_MAC_VLAN_Tag_Data 0x0000000B 0x00000000
R ETHERNET_MAC_VLAN_Hash_Table 0x0000000B 0x00000000
R ETHERNET_MAC_VLAN_Incl 0x0000000B 0x00000000
R ETHERNET_MAC_Inner_VLAN_Incl 0x0000000B 0x00000000
R ETHERNET_MAC_Q0_Tx_Flow_Ctrl 0x0000000B 0x00000000
R ETHERNET_MAC_Rx_Flow_Ctrl 0x0000000B 0x00000000
R ETHERNET_MAC_RxQ_Ctrl4 0x0000000B 0x00000000
R ETHERNET_MAC_RxQ_Ctrl0 0x0000000B 0x0000000A
R ETHERNET_MAC_RxQ_Ctrl1 0x0000000B 0x00000000
R ETHERNET_MAC_RxQ_Ctrl2 0x0000000B 0x00000000
R ETHERNET_MAC_Interrupt_Status 0x0000000B 0x00000000
R ETHERNET_MAC_Interrupt_Enable 0x0000000B 0x00000000
R ETHERNET_MAC_Rx_Tx_Status 0x0000000B 0x00000000
R ETHERNET_MAC_PMT_Control_Status 0x0000000B 0x03000000
R ETHERNET_MAC_RWK_Packet_Filter 0x0000000B 0x00000000
R ETHERNET_MAC_LPI_Control_Status 0x0000000B 0x00000000
R ETHERNET_MAC_LPI_Timers_Control 0x0000000B 0x03E80000
R ETHERNET_MAC_LPI_Entry_Timer 0x0000000B 0x00000000
R ETHERNET_MAC_1US_Tic_Counter 0x0000000B 0x00000063
R ETHERNET_MAC_Version 0x0000000B 0x00000050
R ETHERNET_MAC_Debug 0x0000000B 0x00000000
R ETHERNET_MAC_HW_Feature0 0x0000000B 0x0E1D73F5
R ETHERNET_MAC_HW_Feature1 0x0000000B 0x218E3965
R ETHERNET_MAC_HW_Feature2 0x0000000B 0x22041041
R ETHERNET_MAC_HW_Feature3 0x0000000B 0x00320031
R ETHERNET_MAC_MDIO_Address 0x0000000B 0x0001080C
R ETHERNET_MAC_MDIO_Data 0x0000000B 0x0000FFFF
R ETHERNET_MAC_ARP_Address 0x0000000B 0x00000000
R ETHERNET_MAC_CSR_SW_Ctrl 0x0000000B 0x00000000
R ETHERNET_MAC_Ext_Cfg1 0x0000000B 0x00000002
R ETHERNET_MAC_Address0_High 0x0000000B 0x80008000
R ETHERNET_MAC_Address0_Low 0x0000000B 0x00F263A8
R ETHERNET_MAC_Address1_High 0x0000000B 0x0000FFFF
R ETHERNET_MAC_Address1_Low 0x0000000B 0xFFFFFFFF
R ETHERNET_MAC_Address2_High 0x0000000B 0x0000FFFF
R ETHERNET_MAC_Address2_Low 0x0000000B 0xFFFFFFFF
R ETHERNET_MAC_Address3_High 0x0000000B 0x0000FFFF
R ETHERNET_MAC_Address3_Low 0x0000000B 0xFFFFFFFF
R ETHERNET_MAC_Address4_High 0x0000000B 0x0000FFFF
R ETHERNET_MAC_Address4_Low 0x0000000B 0xFFFFFFFF
R ETHERNET_MAC_Address5_High 0x0000000B 0x0000FFFF
R ETHERNET_MAC_Address5_Low 0x0000000B 0xFFFFFFFF
R ETHERNET_MAC_Address6_High 0x0000000B 0x0000FFFF
R ETHERNET_MAC_Address6_Low 0x0000000B 0xFFFFFFFF
R ETHERNET_MAC_Address7_High 0x0000000B 0x0000FFFF
R ETHERNET_MAC_Address7_Low 0x0000000B 0xFFFFFFFF
R ETHERNET_MMC_Control 0x0000000B 0x00000000
R ETHERNET_MMC_Rx_Interrupt 0x0000000B 0x00000000
R ETHERNET_MMC_Tx_Interrupt 0x0000000B 0x00000000
R ETHERNET_MMC_Rx_Interrupt_Mask 0x0000000B 0x00000000
R ETHERNET_MMC_Tx_Interrupt_Mask 0x0000000B 0x00000000
R ETHERNET_Tx_Octet_Count_Good_Bad 0x0000000B 0x039A9FC8
R ETHERNET_Tx_Packet_Count_Good_Bad 0x0000000B 0x0000D244
R ETHERNET_Tx_Broadcast_Packets_Good 0x0000000B 0x00000190
R ETHERNET_Tx_Multicast_Packets_Good 0x0000000B 0x00000000
R ETHERNET_Tx_64Octets_Packets_Good_Bad 0x0000000B 0x00000018
R ETHERNET_Tx_65To127Octets_Packets_Good_Bad 0x0000000B 0x00000209
R ETHERNET_Tx_128To255Octets_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Tx_256To511Octets_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Tx_512To1023Octets_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Tx_1024ToMaxOctets_Packets_Good_Bad 0x0000000B 0x0000D023
R ETHERNET_Tx_Unicast_Packets_Good_Bad 0x0000000B 0x0000D0B4
R ETHERNET_Tx_Multicast_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Tx_Broadcast_Packets_Good_Bad 0x0000000B 0x00000190
R ETHERNET_Tx_Underflow_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_Single_Collision_Good_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_Multiple_Collision_Good_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_Deferred_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_Late_Collision_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_Excessive_Collision_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_Carrier_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_Octet_Count_Good 0x0000000B 0x039A9FC8
R ETHERNET_Tx_Packet_Count_Good 0x0000000B 0x0000D244
R ETHERNET_Tx_Excessive_Deferral_Error 0x0000000B 0x00000000
R ETHERNET_Tx_Pause_Packets 0x0000000B 0x00000000
R ETHERNET_Tx_VLAN_Packets_Good 0x0000000B 0x00000000
R ETHERNET_Tx_OSize_Packets_Good 0x0000000B 0x00000000
R ETHERNET_Rx_Packets_Count_Good_Bad 0x0000000B 0x00000A8E
R ETHERNET_Rx_Octet_Count_Good_Bad 0x0000000B 0x0002D594
R ETHERNET_Rx_Octet_Count_Good 0x0000000B 0x0002D594
R ETHERNET_Rx_Broadcast_Packets_Good 0x0000000B 0x000000BE
R ETHERNET_Rx_Multicast_Packets_Good 0x0000000B 0x00000000
R ETHERNET_Rx_CRC_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Alignment_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Runt_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Jabber_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Undersize_Packets_Good 0x0000000B 0x00000000
R ETHERNET_Rx_Oversize_Packets_Good 0x0000000B 0x00000000
R ETHERNET_Rx_64Octets_Packets_Good_Bad 0x0000000B 0x000007F7
R ETHERNET_Rx_65To127Octets_Packets_Good_Bad 0x0000000B 0x00000293
R ETHERNET_Rx_128To255Octets_Packets_Good_Bad 0x0000000B 0x00000004
R ETHERNET_Rx_256To511Octets_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Rx_512To1023Octets_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Rx_1024ToMaxOctets_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Rx_Unicast_Packets_Good 0x0000000B 0x000009D0
R ETHERNET_Rx_Length_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Out_Of_Range_Type_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Pause_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_FIFO_Overflow_Packets 0x0000000B 0x00000479
R ETHERNET_Rx_VLAN_Packets_Good_Bad 0x0000000B 0x00000000
R ETHERNET_Rx_Watchdog_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Receive_Error_Packets 0x0000000B 0x00000000
R ETHERNET_Rx_Control_Packets_Good 0x0000000B 0x00000000
R ETHERNET_Tx_LPI_USEC_Cntr 0x0000000B 0x00000000
R ETHERNET_Tx_LPI_Tran_Cntr 0x0000000B 0x00000000
R ETHERNET_Rx_LPI_USEC_Cntr 0x0000000B 0x00000000
R ETHERNET_Rx_LPI_Tran_Cntr 0x0000000B 0x00000000
R ETHERNET_MMC_IPC_Rx_Interrupt_Mask 0x0000000B 0x00000000
R ETHERNET_MMC_IPC_Rx_Interrupt 0x0000000B 0x00000000
R ETHERNET_RxIPv4_Good_Packets 0x0000000B 0x00000A42
R ETHERNET_RxIPv4_Header_Error_Packets 0x0000000B 0x00000000
R ETHERNET_RxIPv4_No_Payload_Packets 0x0000000B 0x00000000
R ETHERNET_RxIPv4_Fragmented_Packets 0x0000000B 0x00000000
R ETHERNET_RxIPv4_UDP_Checksum_Disabled_Packets 0x0000000B 0x00000000
R ETHERNET_RxIPv6_Good_Packets 0x0000000B 0x00000000
R ETHERNET_RxIPv6_Header_Error_Packets 0x0000000B 0x00000000
R ETHERNET_RxIPv6_No_Payload_Packets 0x0000000B 0x00000000
R ETHERNET_RxUDP_Good_Packets 0x0000000B 0x00000836
R ETHERNET_RxUDP_Error_Packets 0x0000000B 0x00000000
R ETHERNET_RxTCP_Good_Packets 0x0000000B 0x00000000
R ETHERNET_RxTCP_Error_Packets 0x0000000B 0x00000000
R ETHERNET_RxICMP_Good_Packets 0x0000000B 0x0000020C
R ETHERNET_RxICMP_Error_Packets 0x0000000B 0x00000000
R ETHERNET_RxIPv4_Good_Octets 0x0000000B 0x0001961F
R ETHERNET_RxIPv4_Header_Error_Octets 0x0000000B 0x00000000
R ETHERNET_RxIPv4_No_Payload_Octets 0x0000000B 0x00000000
R ETHERNET_RxIPv4_Fragmented_Octets 0x0000000B 0x00000000
R ETHERNET_RxIPv4_UDP_Checksum_Disable_Octets 0x0000000B 0x00000000
R ETHERNET_RxIPv6_Good_Octets 0x0000000B 0x00000000
R ETHERNET_RxIPv6_Header_Error_Octets 0x0000000B 0x00000000
R ETHERNET_RxIPv6_No_Payload_Octets 0x0000000B 0x00000000
R ETHERNET_RxUDP_Good_Octets 0x0000000B 0x00007717
R ETHERNET_RxUDP_Error_Octets 0x0000000B 0x00000000
R ETHERNET_RxTCP_Good_Octets 0x0000000B 0x00000000
R ETHERNET_RxTCP_Error_Octets 0x0000000B 0x00000000
R ETHERNET_RxICMP_Good_Octets 0x0000000B 0x000051E0
R ETHERNET_RxICMP_Error_Octets 0x0000000B 0x00000000
R ETHERNET_MAC_L3_L4_Control0 0x0000000B 0x00000000
R ETHERNET_MAC_Layer4_Address0 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr0_Reg0 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr1_Reg0 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr2_Reg0 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr3_Reg0 0x0000000B 0x00000000
R ETHERNET_MAC_L3_L4_Control1 0x0000000B 0x00000000
R ETHERNET_MAC_Layer4_Address1 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr0_Reg1 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr1_Reg1 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr2_Reg1 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr3_Reg1 0x0000000B 0x00000000
R ETHERNET_MAC_L3_L4_Control2 0x0000000B 0x00000000
R ETHERNET_MAC_Layer4_Address2 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr0_Reg2 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr1_Reg2 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr2_Reg2 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr3_Reg2 0x0000000B 0x00000000
R ETHERNET_MAC_L3_L4_Control3 0x0000000B 0x00000000
R ETHERNET_MAC_Layer4_Address3 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr0_Reg3 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr1_Reg3 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr2_Reg3 0x0000000B 0x00000000
R ETHERNET_MAC_Layer3_Addr3_Reg3 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Control 0x0000000B 0x00002000
R ETHERNET_MAC_Sub_Second_Increment 0x0000000B 0x00000000
R ETHERNET_MAC_System_Time_Seconds 0x0000000B 0x00000000
R ETHERNET_MAC_System_Time_Nanoseconds 0x0000000B 0x00000000
R ETHERNET_MAC_System_Time_Seconds_Update 0x0000000B 0x00000000
R ETHERNET_MAC_System_Time_Nanoseconds_Update 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Addend 0x0000000B 0x00000000
R ETHERNET_MAC_System_Time_Higher_Word_Seconds 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Status 0x0000000B 0x00000000
R ETHERNET_MAC_Tx_Timestamp_Status_Nanoseconds 0x0000000B 0x00000000
R ETHERNET_MAC_Tx_Timestamp_Status_Seconds 0x0000000B 0x00000000
R ETHERNET_MAC_Auxiliary_Control 0x0000000B 0x00000000
R ETHERNET_MAC_Auxiliary_Timestamp_Nanoseconds 0x0000000B 0x00000000
R ETHERNET_MAC_Auxiliary_Timestamp_Seconds 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Ingress_Asym_Corr 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Egress_Asym_Corr 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Ingress_Corr_Nanosecond 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Egress_Corr_Nanosecond 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Ingress_Corr_Subnanosec 0x0000000B 0x00000000
R ETHERNET_MAC_Timestamp_Egress_Corr_Subnanosec 0x0000000B 0x00000000
R ETHERNET_MAC_PPS_Control 0x0000000B 0x00000000
R ETHERNET_MAC_PPS0_Target_Time_Seconds 0x0000000B 0x00000000
R ETHERNET_MAC_PPS0_Target_Time_Nanoseconds 0x0000000B 0x00000000
R ETHERNET_MAC_PPS0_Interval 0x0000000B 0x00000000
R ETHERNET_MAC_PPS0_Width 0x0000000B 0x00000000
R ETHERNET_MAC_PPS1_Target_Time_Seconds 0x0000000B 0x00000000
R ETHERNET_MAC_PPS1_Target_Time_Nanoseconds 0x0000000B 0x00000000
R ETHERNET_MAC_PPS1_Interval 0x0000000B 0x00000000
R ETHERNET_MAC_PPS1_Width 0x0000000B 0x00000000
R ETHERNET_MAC_PTO_Control 0x0000000B 0x00000000
R ETHERNET_MAC_Source_Port_Identity0 0x0000000B 0x00000000
R ETHERNET_MAC_Source_Port_Identity1 0x0000000B 0x00000000
R ETHERNET_MAC_Source_Port_Identity2 0x0000000B 0x00000000
R ETHERNET_MAC_Log_Message_Interval 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_IPREVNUM 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_CTRLSTS 0x0000000B 0x00000100
R ETHERNETSS_ETHERNETSS_PTPTSTRIGSEL0 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTPTSTRIGSEL1 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTPTSSWTRIG0 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTPTSSWTRIG1 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTPPPSR0 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTPPPSR1 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTP_TSRL 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTP_TSRH 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTP_TSWL 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_PTP_TSWH 0x0000000B 0x00000000
R ETHERNETSS_ETHERNETSS_REVMII_CTRL 0x0000000B 0x00000000
R FLASHCTRL_FRDCNTL 0x0000000B 0x00000200
R FLASHCTRL_FBAC 0x0000000B 0x0000000F
R FLASHCTRL_FBFALLBACK 0x0000000B 0x00000003
R FLASHCTRL_FBPRDY 0x0000000B 0x00008001
R FLASHCTRL_FPAC1 0x0000000B 0x061A0001
R FLASHCTRL_FMSTAT 0x0000000B 0x00000000
R FLASHCTRL_FRD_INTF_CTRL_LOCK 0x0000000B 0xA5A5A5A5
R FLASHCTRL_FRD_INTF_CTRL 0x0000000B 0x00000003
R FLASHECC_ECC_ENABLE 0x0000000B 0x0000000A
R FLASHECC_SINGLE_ERR_ADDR_LOW 0x0000000B 0x00000000
R FLASHECC_SINGLE_ERR_ADDR_HIGH 0x0000000B 0x00000000
R FLASHECC_UNC_ERR_ADDR_LOW 0x0000000B 0x00000000
R FLASHECC_UNC_ERR_ADDR_HIGH 0x0000000B 0x00000000
R FLASHECC_ERR_STATUS 0x0000000B 0x00000000
R FLASHECC_ERR_POS 0x0000000B 0x00000000
R FLASHECC_ERR_STATUS_CLR 0x0000000B 0x00000000
R FLASHECC_ERR_CNT 0x0000000B 0x00000000
R FLASHECC_ERR_THRESHOLD 0x0000000B 0x00000000
R FLASHECC_ERR_INTFLG 0x0000000B 0x00000000
R FLASHECC_ERR_INTCLR 0x0000000B 0x00000000
R FLASHECC_FDATAH_TEST 0x0000000B 0x00000000
R FLASHECC_FDATAL_TEST 0x0000000B 0x00000000
R FLASHECC_FADDR_TEST 0x0000000B 0x00000000
R FLASHECC_FECC_TEST 0x0000000B 0x00000000
R FLASHECC_FECC_CTRL 0x0000000B 0x00000000
R FLASHECC_FOUTH_TEST 0x0000000B 0x00000000
R FLASHECC_FOUTL_TEST 0x0000000B 0x00000000
R FLASHECC_FECC_STATUS 0x0000000B 0x00000000
R FLASHECC_FLASH_ECC_REGS_LOCK 0x0000000B 0xA5A5A5A5
R GCRC_CRCCTRL 0x0000000B 0x00000220
R GCRC_CRCPOLY 0x0000000B 0x04C11DB7
R GCRC_CRCDATAMASK 0x0000000B 0x00000000
R GCRC_CRCDATAIN 0x0000000B 0x00000000
R GCRC_CRCDATAOUT 0x0000000B 0x00000000
R GCRC_CRCDATATRANS 0x0000000B 0x00000000
R GPIODATA_GPADAT 0x0000000B 0x0FFFFFAB
R GPIODATA_GPASET 0x0000000B 0x00000000
R GPIODATA_GPACLEAR 0x0000000B 0x00000000
R GPIODATA_GPATOGGLE 0x0000000B 0x00000000
R GPIODATA_GPBDAT 0x0000000B 0xFFFFEFFB
R GPIODATA_GPBSET 0x0000000B 0x00000000
R GPIODATA_GPBCLEAR 0x0000000B 0x00000000
R GPIODATA_GPBTOGGLE 0x0000000B 0x00000000
R GPIODATA_GPCDAT 0x0000000B 0xFFFFF7FF
R GPIODATA_GPCSET 0x0000000B 0x00000000
R GPIODATA_GPCCLEAR 0x0000000B 0x00000000
R GPIODATA_GPCTOGGLE 0x0000000B 0x00000000
R GPIODATA_GPDDAT 0x0000000B 0xE2B09DFF
R GPIODATA_GPDSET 0x0000000B 0x00000000
R GPIODATA_GPDCLEAR 0x0000000B 0x00000000
R GPIODATA_GPDTOGGLE 0x0000000B 0x00000000
R GPIODATA_GPEDAT 0x0000000B 0xFFFFFFDF
R GPIODATA_GPESET 0x0000000B 0x00000000
R GPIODATA_GPECLEAR 0x0000000B 0x00000000
R GPIODATA_GPETOGGLE 0x0000000B 0x00000000
R GPIODATA_GPFDAT 0x0000000B 0x000001FF
R GPIODATA_GPFSET 0x0000000B 0x00000000
R GPIODATA_GPFCLEAR 0x0000000B 0x00000000
R GPIODATA_GPFTOGGLE 0x0000000B 0x00000000
R GPIODATAREAD_GPADAT_R 0x0000000B 0x00000000
R GPIODATAREAD_GPBDAT_R 0x0000000B 0x00000000
R GPIODATAREAD_GPCDAT_R 0x0000000B 0x00000000
R GPIODATAREAD_GPDDAT_R 0x0000000B 0x00801000
R GPIODATAREAD_GPEDAT_R 0x0000000B 0x00000000
R GPIODATAREAD_GPFDAT_R 0x0000000B 0x00000000
R GPIODATAREAD_GPGDAT_R 0x0000000B 0x00000000
R GPIODATAREAD_GPHDAT_R 0x0000000B 0x00000000
R I2C0_I2CMSA 0x0000000B 0x00000000
R I2C0_I2CMCS 0x0000000B 0x00000020
R I2C0_I2CMDR 0x0000000B 0x00000000
R I2C0_I2CMTPR 0x0000000B 0x00010001
R I2C0_I2CMIMR 0x0000000B 0x00000000
R I2C0_I2CMRIS 0x0000000B 0x00000000
R I2C0_I2CMMIS 0x0000000B 0x00000000
R I2C0_I2CMICR 0x0000000B 0x00000000
R I2C0_I2CMCR 0x0000000B 0x00000000
R I2C0_I2CMCLKOCNT 0x0000000B 0x00000000
R I2C0_I2CMBMON 0x0000000B 0x00000003
R I2C0_I2CMBLEN 0x0000000B 0x00000000
R I2C0_I2CMBCNT 0x0000000B 0x00000000
R I2C0_I2CSOAR 0x0000000B 0x00000000
R I2C0_I2CSCSR 0x0000000B 0x00000000
R I2C0_I2CSDR 0x0000000B 0x00000000
R I2C0_I2CSIMR 0x0000000B 0x00000000
R I2C0_I2CSRIS 0x0000000B 0x00000000
R I2C0_I2CSMIS 0x0000000B 0x00000000
R I2C0_I2CSICR 0x0000000B 0x00000000
R I2C0_I2CSOAR2 0x0000000B 0x00000000
R I2C0_I2CSACKCTL 0x0000000B 0x00000000
R I2C0_I2CFIFODATARX 0x0000000B 0x00000048
R I2C0_I2CFIFOCTL 0x0000000B 0x00040004
R I2C0_I2CFIFOSTATUS 0x0000000B 0x00010005
R I2C0_I2CPP 0x0000000B 0x00000001
R I2C0_I2CPC 0x0000000B 0x00000001
R IPCCMTOCPU1_CMTOCPU1IPCACK 0x0000000B 0x00000000
R IPCCMTOCPU1_CPU1TOCMIPCSTS 0x0000000B 0x00000000
R IPCCMTOCPU1_CMTOCPU1IPCSET 0x0000000B 0x00000000
R IPCCMTOCPU1_CMTOCPU1IPCCLR 0x0000000B 0x00000000
R IPCCMTOCPU1_CMTOCPU1IPCFLG 0x0000000B 0x00000000
R IPCCMTOCPU1_IPCCOUNTERL 0x0000000B 0xF58FE147
R IPCCMTOCPU1_IPCCOUNTERH 0x0000000B 0x00000099
R IPCCMTOCPU1_CPU1TOCMIPCRECVCOM 0x0000000B 0x00001001
R IPCCMTOCPU1_CPU1TOCMIPCRECVADDR 0x0000000B 0x00000000
R IPCCMTOCPU1_CPU1TOCMIPCRECVDATA 0x0000000B 0x00000440
R IPCCMTOCPU1_CMTOCPU1IPCREPLY 0x0000000B 0x00005555
R IPCCMTOCPU1_CMTOCPU1IPCSENDCOM 0x0000000B 0x00001001
R IPCCMTOCPU1_CMTOCPU1IPCSENDADDR 0x0000000B 0x00000000
R IPCCMTOCPU1_CMTOCPU1IPCSENDDATA 0x0000000B 0x00000002
R IPCCMTOCPU1_CPU1TOCMIPCREPLY 0x0000000B 0x00005555
R IPCCMTOCPU1_CMTOCPU1IPCBOOTSTS 0x0000000B 0x80001002
R IPCCMTOCPU1_CPU1TOCMIPCBOOTMODE 0x0000000B 0x5A007D03
R IPCCMTOCPU1_PUMPREQUEST 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCACK 0x0000000B 0x00000000
R IPCCMTOCPU2_CPU2TOCMIPCSTS 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCSET 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCCLR 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCFLG 0x0000000B 0x00000000
R IPCCMTOCPU2_IPCCOUNTERL 0x0000000B 0xECD0704D
R IPCCMTOCPU2_IPCCOUNTERH 0x0000000B 0x00000099
R IPCCMTOCPU2_CPU2TOCMIPCRECVCOM 0x0000000B 0x00000000
R IPCCMTOCPU2_CPU2TOCMIPCRECVADDR 0x0000000B 0x00000000
R IPCCMTOCPU2_CPU2TOCMIPCRECVDATA 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCREPLY 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCSENDCOM 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCSENDADDR 0x0000000B 0x00000000
R IPCCMTOCPU2_CMTOCPU2IPCSENDDATA 0x0000000B 0x00000000
R IPCCMTOCPU2_CPU2TOCMIPCREPLY 0x0000000B 0x00000000
R MCANSS_MCANSS_PID 0x0000000B 0x68E03901
R MCANSS_MCANSS_CTRL 0x0000000B 0x00000008
R MCANSS_MCANSS_STAT 0x0000000B 0x00000006
R MCANSS_MCANSS_ICS 0x0000000B 0x00000000
R MCANSS_MCANSS_IRS 0x0000000B 0x00000000
R MCANSS_MCANSS_IECS 0x0000000B 0x00000000
R MCANSS_MCANSS_IE 0x0000000B 0x00000000
R MCANSS_MCANSS_IES 0x0000000B 0x00000000
R MCANSS_MCANSS_EOI 0x0000000B 0x00000000
R MCANSS_MCANSS_EXT_TS_PRESCALER 0x0000000B 0x00000000
R MCANSS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR 0x0000000B 0x00000000
R MCAN_MCAN_CREL 0x0000000B 0x32270530
R MCAN_MCAN_ENDN 0x0000000B 0x87654321
R MCAN_MCAN_DBTP 0x0000000B 0x00000A33
R MCAN_MCAN_TEST 0x0000000B 0x00000000
R MCAN_MCAN_RWD 0x0000000B 0x00000000
R MCAN_MCAN_CCCR 0x0000000B 0x00000001
R MCAN_MCAN_NBTP 0x0000000B 0x06000A03
R MCAN_MCAN_TSCC 0x0000000B 0x00000000
R MCAN_MCAN_TSCV 0x0000000B 0x00000000
R MCAN_MCAN_TOCC 0x0000000B 0xFFFF0000
R MCAN_MCAN_TOCV 0x0000000B 0x0000FFFF
R MCAN_MCAN_ECR 0x0000000B 0x00000000
R MCAN_MCAN_PSR 0x0000000B 0x00000707
R MCAN_MCAN_TDCR 0x0000000B 0x00000000
R MCAN_MCAN_IR 0x0000000B 0x00000000
R MCAN_MCAN_IE 0x0000000B 0x00000000
R MCAN_MCAN_ILS 0x0000000B 0x00000000
R MCAN_MCAN_ILE 0x0000000B 0x00000000
R MCAN_MCAN_GFC 0x0000000B 0x00000000
R MCAN_MCAN_SIDFC 0x0000000B 0x00000000
R MCAN_MCAN_XIDFC 0x0000000B 0x00000000
R MCAN_MCAN_XIDAM 0x0000000B 0x1FFFFFFF
R MCAN_MCAN_HPMS 0x0000000B 0x00000000
R MCAN_MCAN_NDAT1 0x0000000B 0x00000000
R MCAN_MCAN_NDAT2 0x0000000B 0x00000000
R MCAN_MCAN_RXF0C 0x0000000B 0x00000000
R MCAN_MCAN_RXF0S 0x0000000B 0x00000000
R MCAN_MCAN_RXF0A 0x0000000B 0x00000000
R MCAN_MCAN_RXBC 0x0000000B 0x00000000
R MCAN_MCAN_RXF1C 0x0000000B 0x00000000
R MCAN_MCAN_RXF1S 0x0000000B 0x00000000
R MCAN_MCAN_RXF1A 0x0000000B 0x00000000
R MCAN_MCAN_RXESC 0x0000000B 0x00000000
R MCAN_MCAN_TXBC 0x0000000B 0x00000000
R MCAN_MCAN_TXFQS 0x0000000B 0x00000000
R MCAN_MCAN_TXESC 0x0000000B 0x00000000
R MCAN_MCAN_TXBRP 0x0000000B 0x00000000
R MCAN_MCAN_TXBAR 0x0000000B 0x00000000
R MCAN_MCAN_TXBCR 0x0000000B 0x00000000
R MCAN_MCAN_TXBTO 0x0000000B 0x00000000
R MCAN_MCAN_TXBCF 0x0000000B 0x00000000
R MCAN_MCAN_TXBTIE 0x0000000B 0x00000000
R MCAN_MCAN_TXBCIE 0x0000000B 0x00000000
R MCAN_MCAN_TXEFC 0x0000000B 0x00000000
R MCAN_MCAN_TXEFS 0x0000000B 0x00000000
R MCAN_MCAN_TXEFA 0x0000000B 0x00000000
R MCANERR_MCANERR_REV 0x0000000B 0x66A0E200
R MCANERR_MCANERR_VECTOR 0x0000000B 0x00000000
R MCANERR_MCANERR_STAT 0x0000000B 0x00000002
R MCANERR_MCANERR_WRAP_REV 0x0000000B 0x00000000
R MCANERR_MCANERR_CTRL 0x0000000B 0x00000000
R MCANERR_MCANERR_ERR_CTRL1 0x0000000B 0x00000000
R MCANERR_MCANERR_ERR_CTRL2 0x0000000B 0x00000000
R MCANERR_MCANERR_ERR_STAT1 0x0000000B 0x00000000
R MCANERR_MCANERR_ERR_STAT2 0x0000000B 0x00000000
R MCANERR_MCANERR_ERR_STAT3 0x0000000B 0x00000000
R MCANERR_MCANERR_SEC_EOI 0x0000000B 0x00000000
R MCANERR_MCANERR_SEC_STATUS 0x0000000B 0x00000000
R MCANERR_MCANERR_SEC_ENABLE_SET 0x0000000B 0x00000000
R MCANERR_MCANERR_SEC_ENABLE_CLR 0x0000000B 0x00000000
R MCANERR_MCANERR_DED_EOI 0x0000000B 0x00000000
R MCANERR_MCANERR_DED_STATUS 0x0000000B 0x00000000
R MCANERR_MCANERR_DED_ENABLE_SET 0x0000000B 0x00000000
R MCANERR_MCANERR_DED_ENABLE_CLR 0x0000000B 0x00000000
R MCANERR_MCANERR_AGGR_ENABLE_SET 0x0000000B 0x00000000
R MCANERR_MCANERR_AGGR_ENABLE_CLR 0x0000000B 0x00000000
R MCANERR_MCANERR_AGGR_STATUS_SET 0x0000000B 0x00000000
R MCANERR_MCANERR_AGGR_STATUS_CLR 0x0000000B 0x00000000
R MEMINITANDTEST_CxLOCK 0x0000000B 0x00000000
R MEMINITANDTEST_CxTEST 0x0000000B 0x00000000
R MEMINITANDTEST_CxINIT 0x0000000B 0x00000000
R MEMINITANDTEST_CxINITDONE 0x0000000B 0x00000000
R MEMINITANDTEST_CMMSGxLOCK 0x0000000B 0x00000000
R MEMINITANDTEST_CMMSGxTEST 0x0000000B 0x00000000
R MEMINITANDTEST_CMMSGxINIT 0x0000000B 0x00000000
R MEMINITANDTEST_CMMSGxINITDONE 0x0000000B 0x00000000
R MEMINITANDTEST_SxGROUP1_LOCK 0x0000000B 0x00000000
R MEMINITANDTEST_SxGROUP1_TEST 0x0000000B 0x00000000
R MEMINITANDTEST_SxGROUP1_INIT 0x0000000B 0x00000000
R MEMINITANDTEST_SxGROUP1_INITDONE 0x0000000B 0x00000000
R MEMINITANDTEST_ROM_LOCK 0x0000000B 0x00000000
R MEMINITANDTEST_ROM_TEST 0x0000000B 0x00000000
R MEMINITANDTEST_ROM_FORCE_ERROR 0x0000000B 0x00000000
R MEMINITANDTEST_PERI_MEM_TEST_LOCK 0x0000000B 0x00000000
R MEMINITANDTEST_PERI_MEM_TEST_CONTROL 0x0000000B 0x00000000
R MPU_MPU_TYPE 0x0000000B 0x00000800
R MPU_MPU_CTRL 0x0000000B 0x00000000
R MPU_MPU_RNR 0x0000000B 0x00000000
R MPU_MPU_RBAR 0x0000000B 0x00000000
R MPU_MPU_RASR 0x0000000B 0x00000000
R MPU_MPU_RBAR_A1 0x0000000B 0x00000000
R MPU_MPU_RASR_A1 0x0000000B 0x00000000
R MPU_MPU_RBAR_A2 0x0000000B 0x00000000
R MPU_MPU_RASR_A2 0x0000000B 0x00000000
R MPU_MPU_RBAR_A3 0x0000000B 0x00000000
R MPU_MPU_RASR_A3 0x0000000B 0x00000000
R NMI_CMNMICFG 0x0000000B 0x00000001
R NMI_CMNMIFLG 0x0000000B 0x00000000
R NMI_CMNMIFLGCLR 0x0000000B 0x00000000
R NMI_CMNMIFLGFRC 0x0000000B 0x00000000
R NMI_CMNMIWDCNT 0x0000000B 0x00000000
R NMI_CMNMIWDPRD 0x0000000B 0x0000FFFF
R NMI_CMNMISHDWFLG 0x0000000B 0x00000000
R NVIC_NVIC_ISER0 0x0000000B 0x20014000
R NVIC_NVIC_ISER1 0x0000000B 0x00000000
R NVIC_NVIC_ICER0 0x0000000B 0x20014000
R NVIC_NVIC_ICER1 0x0000000B 0x00000000
R NVIC_NVIC_ISPR0 0x0000000B 0x00002000
R NVIC_NVIC_ISPR1 0x0000000B 0x00000000
R NVIC_NVIC_ISPR2 0x0000000B 0x00000000
R NVIC_NVIC_ICPR0 0x0000000B 0x00002000
R NVIC_NVIC_ICPR1 0x0000000B 0x00000000
R NVIC_NVIC_IABR0 0x0000000B 0x00000000
R NVIC_NVIC_IABR1 0x0000000B 0x00000000
R NVIC_NVIC_IPR0 0x0000000B 0x00000000
R NVIC_NVIC_IPR1 0x0000000B 0x00000000
R NVIC_NVIC_IPR2 0x0000000B 0x00000000
R NVIC_NVIC_IPR3 0x0000000B 0x00000000
R NVIC_NVIC_IPR4 0x0000000B 0x00000000
R NVIC_NVIC_IPR5 0x0000000B 0x00000000
R NVIC_NVIC_IPR6 0x0000000B 0x00000000
R NVIC_NVIC_IPR7 0x0000000B 0x00000000
R NVIC_NVIC_IPR8 0x0000000B 0x00000000
R NVIC_NVIC_IPR9 0x0000000B 0x00000000
R NVIC_NVIC_IPR10 0x0000000B 0x00000000
R NVIC_NVIC_IPR11 0x0000000B 0x00000000
R NVIC_NVIC_IPR12 0x0000000B 0x00000000
R NVIC_NVIC_IPR13 0x0000000B 0x00000000
R NVIC_NVIC_IPR14 0x0000000B 0x00000000
R NVIC_NVIC_IPR15 0x0000000B 0x00000000
R NVIC_STIR 0x0000000B 0x00000000
R SSI0_SSICR0 0x0000000B 0x00000000
R SSI0_SSICR1 0x0000000B 0x00000000
R SSI0_SSIDR 0x0000000B 0x00000000
R SSI0_SSISR 0x0000000B 0x00000003
R SSI0_SSICPSR 0x0000000B 0x00000000
R SSI0_SSIIM 0x0000000B 0x00000000
R SSI0_SSIRIS 0x0000000B 0x00000008
R SSI0_SSIMIS 0x0000000B 0x00000000
R SSI0_SSIICR 0x0000000B 0x00000000
R SSI0_SSIDMACTL 0x0000000B 0x00000000
R SSI0_SSIPV 0x0000000B 0x00000000
R SSI0_SSIPP 0x0000000B 0x00000009
R SSI0_SSIPC 0x0000000B 0x00000000
R SSI0_SSIPeriphID4 0x0000000B 0x00000000
R SSI0_SSIPeriphID5 0x0000000B 0x00000000
R SSI0_SSIPeriphID6 0x0000000B 0x00000000
R SSI0_SSIPeriphID7 0x0000000B 0x00000000
R SSI0_SSIPeriphID0 0x0000000B 0x00000022
R SSI0_SSIPeriphID1 0x0000000B 0x00000000
R SSI0_SSIPeriphID2 0x0000000B 0x00000018
R SSI0_SSIPeriphID3 0x0000000B 0x00000001
R SSI0_SSIPCellID0 0x0000000B 0x0000000D
R SSI0_SSIPCellID1 0x0000000B 0x000000F0
R SSI0_SSIPCellID2 0x0000000B 0x00000005
R SSI0_SSIPCellID3 0x0000000B 0x000000B1
R CMSYSCTL_CMPCLKCR0 0x0000000B 0x00001111
R CMSYSCTL_CMPCLKCR1 0x0000000B 0x00000135
R CMSYSCTL_CMPCLKCR2 0x0000000B 0x00000157
R CMSYSCTL_CMSOFTPRESET0 0x0000000B 0x00000000
R CMSYSCTL_CMSOFTPRESET1 0x0000000B 0x00000004
R CMSYSCTL_CMSOFTPRESET2 0x0000000B 0x00000000
R CMSYSCTL_CMCLKSTOPREQ0 0x0000000B 0x00000000
R CMSYSCTL_CMCLKSTOPREQ1 0x0000000B 0x00000000
R CMSYSCTL_CMCLKSTOPREQ2 0x0000000B 0x00000000
R CMSYSCTL_CMCLKSTOPACK0 0x0000000B 0x00000000
R CMSYSCTL_CMCLKSTOPACK1 0x0000000B 0x00000000
R CMSYSCTL_CMCLKSTOPACK2 0x0000000B 0x00000000
R CMSYSCTL_MCANWAKESTATUS 0x0000000B 0x00000000
R CMSYSCTL_MCANWAKESTATUSCLR 0x0000000B 0x00000000
R CMSYSCTL_CMECATCTL 0x0000000B 0x00000000
R CMSYSCTL_PALLOCATESTS 0x0000000B 0x00000010
R CMSYSCTL_CMRESCCLR 0x0000000B 0x00000000
R CMSYSCTL_CMRESC 0x0000000B 0x00000112
R CMSYSCTL_CMSYSCTLLOCK 0x0000000B 0x00000000
R SCB_ACTLR 0x0000000B 0x00000000
R SCB_CPUID 0x0000000B 0x410FC241
R SCB_ICSR 0x0000000B 0x00400000
R SCB_VTOR 0x0000000B 0x20011400
R SCB_AIRCR 0x0000000B 0xFA050000
R SCB_SCR 0x0000000B 0x00000000
R SCB_CCR 0x0000000B 0x00000200
R SCB_SHPR1 0x0000000B 0x00000000
R SCB_SHPR2 0x0000000B 0x00000000
R SCB_SHPR3 0x0000000B 0x00000000
R SCB_SHCSRS 0x0000000B 0x00000000
R SCB_CFSR 0x0000000B 0x00000000
R SCB_HFSR 0x0000000B 0x00000000
R SCB_MMFAR 0x0000000B 0x20011286
R SCB_BFAR 0x0000000B 0x20011286
R SCB_AFSR 0x0000000B 0x00000000
R SYSTICK_SYST_CSR 0x0000000B 0x00010007
R SYSTICK_SYST_RVR 0x0000000B 0x00E4E1BF
R SYSTICK_SYST_CVR 0x0000000B 0x008557DC
R SYSTICK_SYST_CALIB 0x0000000B 0x80000000
R TIMER0_TIM 0x0000000B 0x0000B514
R TIMER0_PRD 0x0000000B 0x0000FFFF
R TIMER0_TCR 0x0000000B 0x00008001
R TIMER0_TPR 0x0000000B 0x00000000
R TIMER1_TIM 0x0000000B 0x000058BD
R TIMER1_PRD 0x0000000B 0x0000FFFF
R TIMER1_TCR 0x0000000B 0x00008001
R TIMER1_TPR 0x0000000B 0x00000000
R TIMER2_TIM 0x0000000B 0x000015B1
R TIMER2_PRD 0x0000000B 0x0000FFFF
R TIMER2_TCR 0x0000000B 0x00008001
R TIMER2_TPR 0x0000000B 0x00000000
R UART0_UARTECR 0x0000000B 0x00000000
R UDMA_DMASTAT 0x0000000B 0x001F0000
R UDMA_DMACFG 0x0000000B 0x00000000
R UDMA_DMACTLBASE 0x0000000B 0x00000000
R UDMA_DMAALTBASE 0x0000000B 0x00000200
R UDMA_DMASWREQ 0x0000000B 0x00000000
R UDMA_DMAUSEBURSTSET 0x0000000B 0x00000000
R UDMA_DMAUSEBURSTCLR 0x0000000B 0x00000000
R UDMA_DMAREQMASKSET 0x0000000B 0x00000000
R UDMA_DMAREQMASKCLR 0x0000000B 0x00000000
R UDMA_DMAENASET 0x0000000B 0x00000000
R UDMA_DMAENACLR 0x0000000B 0x00000000
R UDMA_DMAALTSET 0x0000000B 0x00000000
R UDMA_DMAALTCLR 0x0000000B 0x00000000
R UDMA_DMAPRIOSET 0x0000000B 0x00000000
R UDMA_DMAPRIOCLR 0x0000000B 0x00000000
R UDMA_DMAERRCLR 0x0000000B 0x00000000
R UDMA_DMACHMAP0 0x0000000B 0x00000000
R UDMA_DMACHMAP1 0x0000000B 0x00000000
R UDMA_DMACHMAP2 0x0000000B 0x00000000
R UDMA_DMACHMAP3 0x0000000B 0x00000000
R UDMA_DMAPeriphID4 0x0000000B 0x00000004
R UDMA_DMAPeriphID0 0x0000000B 0x00000030
R UDMA_DMAPeriphID1 0x0000000B 0x000000B2
R UDMA_DMAPeriphID2 0x0000000B 0x0000000B
R UDMA_DMAPeriphID3 0x0000000B 0x00000000
R UDMA_DMAPCellID0 0x0000000B 0x0000000D
R UDMA_DMAPCellID1 0x0000000B 0x000000F0
R UDMA_DMAPCellID2 0x0000000B 0x00000005
R UDMA_DMAPCellID3 0x0000000B 0x000000B1
R WDT_SCSR 0x0000000B 0x00000003
R WDT_WDCNTR 0x0000000B 0x00000000
R WDT_WDKEY 0x0000000B 0x00000040
R WDT_WDCR 0x0000000B 0x00000040
R WDT_WDWCR 0x0000000B 0x00000000

//###########################################################################
//
// FILE:   f2838xif.c
//
// TITLE:  F2838x interface port file.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright: $
//###########################################################################

/**
 * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 * This file is part of the lwIP TCP/IP stack.
 *
 * Author: Adam Dunkels <adam@sics.se>
 *
 */

/**
 * Copyright (c) 2018 Texas Instruments Incorporated
 *
 * This file is dervied from the ``ethernetif.c'' skeleton Ethernet network
 * interface driver for lwIP.
 *
 */

#include <string.h>
/**
 * lwIP specific header files
 */
#include "lwip/opt.h"
#include "lwip/def.h"
#include "lwip/mem.h"
#include "lwip/pbuf.h"
#include "lwip/sys.h"
#include <lwip/stats.h>
#include <lwip/snmp.h>
#include "netif/etharp.h"
#include "netif/ppp/pppoe.h"
#include "netif/f2838xif.h"

/**
 * f2838x device specific header files
 */
#include "inc/hw_emac.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib_cm/ethernet.h"
#include "driverlib_cm/interrupt.h"
#include "driverlib_cm/sysctl.h"

#include "utils/lwiplib.h"
/**
 * Sanity Check:  This interface driver will NOT work if the following defines
 * are incorrect.
 *
 */
#if (PBUF_LINK_HLEN != 16)
#error "PBUF_LINK_HLEN must be 16 for this interface driver!"
#endif
#if (ETH_PAD_SIZE != 0)
#error "ETH_PAD_SIZE must be 0 for this interface driver!"
#endif
#if (!SYS_LIGHTWEIGHT_PROT)
#error "SYS_LIGHTWEIGHT_PROT must be enabled for this interface driver!"
#endif

/**
 * Number of pbufs supported in low-level tx/rx pbuf queue.
 *
 */
#ifndef F2838X_NUM_PBUF_QUEUE
#define F2838X_NUM_PBUF_QUEUE    20
#endif

#define EMAC_BASE                   0x400C0000U //EMAC
#define EMAC_SS_BASE                0x400C2000U //EMACSS

/* Define those to better describe your network interface. */
#define IFNAME0 't'
#define IFNAME1 'i'

/* Helper struct to hold a queue of pbufs for transmit and receive. */
struct pbufq
{
    struct pbuf *pbuf[F2838X_NUM_PBUF_QUEUE];
    unsigned long qwrite;
    unsigned long qread;
    unsigned long overflow;
};

/* Helper macros for accessing pbuf queues. */
#define PBUF_QUEUE_EMPTY(q) \
    (((q)->qwrite == (q)->qread) ? true : false)

#define PBUF_QUEUE_FULL(q) \
    ((((((q)->qwrite + 1) % F2838X_NUM_PBUF_QUEUE)) == (q)->qread) ? \
    true : false )

/**
 * Helper struct to hold private data used to operate your ethernet interface.
 * Keeping the ethernet address of the MAC in this struct is not necessary
 * as it is already kept in the struct netif.
 * But this is only an example, anyway...
 */
struct f2838xif
{
    struct eth_addr *ethaddr;
    /* Add whatever per-interface state that is needed here. */
    struct pbufq txq;
    Ethernet_Pkt_Desc *pktDesc;
};

/**
 * A structure used to keep track of driver state and error counts.
 */
typedef struct {
    uint32_t ui32TXCount;
    uint32_t ui32TXCopyCount;
    uint32_t ui32TXCopyFailCount;
    uint32_t ui32TXNoDescCount;
    uint32_t ui32TXBufQueuedCount;
    uint32_t ui32TXBufFreedCount;
    uint32_t ui32RXBufReadCount;
    uint32_t ui32RXPacketReadCount;
    uint32_t ui32RXPacketErrCount;
    uint32_t ui32RXPacketCBErrCount;
    uint32_t ui32RXNoBufCount;
}
tDriverStats;

tDriverStats g_sDriverStats = {0};

#define DRIVER_STATS_INC(x) do{ g_sDriverStats.ui32##x++; } while(0)
#define DRIVER_STATS_DEC(x) do{ g_sDriverStats.ui32##x--; } while(0)
#define DRIVER_STATS_ADD(x, inc) do{ g_sDriverStats.ui32##x += inc; } while(0)
#define DRIVER_STATS_SUB(x, dec) do{ g_sDriverStats.ui32##x -= dec; } while(0)

/*
 * Creating a queue that maps an ethernet packet descriptor with
 * the corresponding pbuf. It is useful to free up the allocated pbuf memory
 * after the packet has been sent.
 */
#ifndef F2838X_INTERFACE_NUM_PKT_DESC_QUEUE
#define F2838X_INTERFACE_NUM_PKT_DESC_QUEUE    20
#endif

/**
 * Global variable for this interface's private data.  Needed to allow
 * the interrupt handlers access to this information outside of the
 * context of the lwIP netif.
 *
 */
static struct f2838xif f2838xif_data;

Ethernet_Handle emac_handle;

/**
 * A macro which determines whether a pointer is within the SRAM address
 * space and, hence, points to a buffer that the Ethernet MAC can directly
 * DMA from.
 */
#define PTR_SAFE_FOR_EMAC_DMA(ptr) (((uint32_t)(ptr) >= 0x2000800) &&   \
                                    ((uint32_t)(ptr) < 0x2000FFFF))

/**
 * In this function, the hardware should be initialized.
 * Called from f2838xif_init().
 *
 * @param netif the already initialized lwip network interface structure
 *        for this ethernetif
 */
static void
f2838xif_hwinit(struct netif *netif)
{
    uint32_t mac_low,mac_high;
    uint8_t *pucTemp;

    /* set MAC hardware address length */
    netif->hwaddr_len = ETHARP_HWADDR_LEN;

    /* set MAC address */
    Ethernet_getMACAddr(EMAC_BASE, 0, &mac_high, &mac_low);

    pucTemp = (uint8_t *)&mac_low;
    netif->hwaddr[0] = pucTemp[0];
    netif->hwaddr[1] = pucTemp[1];
    netif->hwaddr[2] = pucTemp[2];
    netif->hwaddr[3] = pucTemp[3];

    pucTemp = (uint8_t *)&mac_high;
    netif->hwaddr[4] = pucTemp[0];
    netif->hwaddr[5] = pucTemp[1];

    /* maximum transfer unit */
    netif->mtu = 1500;

    /* device capabilities */
    /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
    netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_IGMP;
}

/**
 * This function should do the actual transmission of the packet. The packet is
 * contained in the pbuf that is passed to the function. This pbuf might be
 * chained.
 *
 * @param netif the lwip network interface structure for this ethernetif
 * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
 * @return ERR_OK if the packet could be sent
 *         an err_t value if the packet couldn't be sent
 * @note This function MUST be called with interrupts disabled or with the
 *       F2838x Ethernet transmit fifo protected.
 */
static err_t
f2838xif_transmit(struct netif *netif, struct pbuf *p)
{
    struct pbuf *q;

    /* No of pbufs (if chained)*/
    int n=0;
    int i=0;
    Ethernet_Pkt_Desc *pktDescOrigPtr, *pktDescPtr;

    /* ENTER CRITICAL SECTION
     * This is to protect the forming of packetc descriptor chain using pbufs
     * passed to the function.
     */
    Interrupt_disable(INT_EMAC_TX0);
    Interrupt_disable(INT_EMAC_RX0);

    /*
     * Make sure we still have a valid buffer (it may have been copied)
     */
    if(!p)
    {
        LINK_STATS_INC(link.memerr);

        /* EXIT CRITICAL SECTION */
        Interrupt_enable(INT_EMAC_TX0);
        Interrupt_enable(INT_EMAC_RX0);

        return(ERR_MEM);
    }

    /*
     * Count the number of the pbufs in the chain that we are passed with.
     */
    for(q = p; q != NULL; q = q->next)
            n++;

    /*
     * Get the head of the packet descriptor chain that will be passed to
     * the driver for sending.
     */
    pktDescOrigPtr = mem_malloc(sizeof(Ethernet_Pkt_Desc));
    if(pktDescOrigPtr == NULL)
    {
        __asm("   bkpt #0");
    }

    /*
     * Go over the pbufs present in the chain and allot a packet descriptor for
     * each pbuf. The descriptors will also be chained in the same order as
     * pbufs before passing the head of the chain to the driver.
     */
    for(q = p, pktDescPtr = pktDescOrigPtr; // Initialization
        q != NULL; // Condition evaluation
        q = q->next, pktDescPtr = pktDescPtr->nextPacketDesc) // Manipulation
    {
        /*
         * Initializing this data structure, otherwise garbage values will
         * result in rogue results while running.
         */
        memset(pktDescPtr,0,sizeof(Ethernet_Pkt_Desc));

        pktDescPtr->dataOffset = 0;
        pktDescPtr->dataBuffer = q->payload;
        pktDescPtr->pktChannel = ETHERNET_DMA_CHANNEL_NUM_0;
        pktDescPtr->pktLength = q->tot_len;
        pktDescPtr->bufferLength = q->len;
        pktDescPtr->validLength = q->len;


          if(i==0)
          {
                if(n!=1)
                {
                    /*
                     * Prepare the next ethernet packet descriptor holder if
                     * there is a pbuf next in the chain.
                     */
                    pktDescPtr->nextPacketDesc =
                            mem_malloc(sizeof(Ethernet_Pkt_Desc));
                    if(pktDescPtr->nextPacketDesc == NULL)
                        {
                            __asm("   bkpt #0");
                        }
                    pktDescPtr->flags = ETHERNET_PKT_FLAG_SOP ;
                }
                else
                {
                    pktDescPtr->nextPacketDesc = 0;
                    pktDescPtr->flags = ETHERNET_PKT_FLAG_SOP |
                                        ETHERNET_PKT_FLAG_EOP;
                }
          }
          else
          {
              if(q->next != NULL)
              {
                  /*
                   * Prepare the next ethernet packet descriptor holder if
                   * there is a pbuf next in the chain.
                   */
                  pktDescPtr->nextPacketDesc =
                          mem_malloc(sizeof(Ethernet_Pkt_Desc));
                  if(pktDescPtr->nextPacketDesc == NULL)
                      {
                          __asm("   bkpt #0");
                      }
                  pktDescPtr->flags = 0;
              }
              else
              {
                  pktDescPtr->nextPacketDesc = 0;
                  pktDescPtr->flags = ETHERNET_PKT_FLAG_EOP;
              }
          }

          i++;
    }

    /* EXIT CRITICAL SECTION */
    Interrupt_enable(INT_EMAC_TX0);
    Interrupt_enable(INT_EMAC_RX0);

    /*
     * Hand over the packet descriptor to the driver.
     */
    pktDescOrigPtr->numPktFrags = n;
    Ethernet_sendPacket(emac_handle,pktDescOrigPtr);

    LINK_STATS_INC(link.xmit);

    return(ERR_OK);
}

/**
 * This function will process all transmit descriptors and free pbufs attached
 * to any that have been transmitted since we last checked.
 *
 * This function is called only from the Ethernet interrupt handler.
 *
 * @param netif the lwip network interface structure for this ethernetif
 * @return None.
 */
int descriptorFreeErr=0;
static void
f2838xif_process_transmit(struct netif *netif, Ethernet_Pkt_Desc *pPacket)
{
    Ethernet_Pkt_Desc *pktDescPtr, *pktDescPtrShadow;

    /*
     * Free the packet descriptor memory.
     */
    if (pPacket == 0)
        return;

    pktDescPtr = pPacket;

    do
    {
        pktDescPtrShadow = pktDescPtr->nextPacketDesc;
        mem_free(pktDescPtr);
        pktDescPtr = pktDescPtrShadow;
    }
    while(pktDescPtr != 0);

}

/**
 * This function with either place the packet into the F2838x transmit fifo,
 * or will place the packet in the interface PBUF Queue for subsequent
 * transmission when the transmitter becomes idle.
 *
 * @param netif the lwip network interface structure for this ethernetif
 * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
 * @return ERR_OK if the packet could be sent
 *         an err_t value if the packet couldn't be sent
 *
 */

static err_t
f2838xif_output(struct netif *netif, struct pbuf *p)
{
    f2838xif_transmit(netif, p);

    return ERR_OK;
}

/**
 * This function will read a single packet from the F2838x ethernet
 * interface, if available, and return a pointer to a pbuf.  The timestamp
 * of the packet will be placed into the pbuf structure.
 *
 * @param netif the lwip network interface structure for this ethernetif
 * @return pointer to pbuf packet if available, NULL otherswise.
 */
Ethernet_Pkt_Desc*
f2838xif_receive( struct netif *netif, Ethernet_Pkt_Desc *pPacket )
{
    struct pbuf *p;

#if LWIP_PTPD
    u32_t time_s, time_ns;
    /* Get the current timestamp if PTPD is enabled */
    lwIPHostGetTime(&time_s, &time_ns);
#endif

    p = pbuf_alloc(PBUF_RAW, sizeof(struct pbuf), PBUF_POOL);
    if(p)
    {
        p->payload = pPacket->dataBuffer;

        p->len = pPacket->pktLength;
        p->tot_len = p->len;

    #if LWIP_PTPD
        /* Place the timestamp in the PBUF */
        p->time_s = time_s;
        p->time_ns = time_ns;
    #endif

        if(ethernet_input(p, netif)!=ERR_OK)
        {
            /* drop the packet */
            LWIP_DEBUGF(NETIF_DEBUG, ("f2838xif_input: input error\n"));

            /* Adjust the link statistics */
            LINK_STATS_INC(link.memerr);
            LINK_STATS_INC(link.drop);
        }
        pbuf_free(p);
        p = NULL;

    }
    if(pPacket->dataBuffer != NULL)
            memp_free(MEMP_PBUF_POOL, pPacket->dataBuffer);
    if(pPacket != NULL)
        mem_free(pPacket);


    Ethernet_Pkt_Desc *newPacket = mem_calloc(1, sizeof(Ethernet_Pkt_Desc));

    if(newPacket)
       newPacket->dataBuffer = memp_malloc(MEMP_PBUF_POOL);

    LINK_STATS_INC(link.recv);
    return(newPacket);
}

Ethernet_Pkt_Desc *f2838xif_newbuffcallback(void)
{
    Ethernet_Pkt_Desc *newPacket = mem_calloc(1, sizeof(Ethernet_Pkt_Desc));

    if(newPacket)
    {
        newPacket->dataBuffer= memp_malloc(MEMP_PBUF_POOL);
    }
    return newPacket;
}

/**
 * Should be called at the beginning of the program to set up the
 * network interface. It calls the function f2838xif_hwinit() to do the
 * actual setup of the hardware.
 * This function should be passed as a parameter to netif_add().
 *
 * @param netif the lwip network interface structure for this ethernetif
 * @return ERR_OK if the loopif is initialized
 *         ERR_MEM if private data couldn't be allocated
 *         any other err_t on error
 */
err_t
f2838xif_init(struct netif *netif)
{
    LWIP_ASSERT("netif != NULL", (netif != NULL));

#if LWIP_NETIF_HOSTNAME
    /* Initialize interface hostname */
    netif->hostname = "lwip";
#endif /* LWIP_NETIF_HOSTNAME */

    /*
     * Initialize the snmp variables and counters inside the struct netif.
     * The last argument should be replaced with your link speed, in units
     * of bits per second.
     */
    NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 1000000);

    netif->state = &f2838xif_data;
    netif->name[0] = IFNAME0;
    netif->name[1] = IFNAME1;

    /* We directly use etharp_output() here to save a function call.
     * You can instead declare your own function an call etharp_output()
     * from it if you have to do some checks before sending (e.g. if link
     * is available...) */
    netif->output = etharp_output;
    netif->linkoutput = f2838xif_output;

    f2838xif_data.ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
    f2838xif_data.txq.qread = f2838xif_data.txq.qwrite = 0;
    f2838xif_data.txq.overflow = 0;

    /* initialize the hardware */
    f2838xif_hwinit(netif);

    return ERR_OK;
}

/**
 * Process tx and rx packets at the low-level interrupt.
 *
 * Should be called from the F2838x Ethernet Interrupt Handler.  This
 * function will read packets from the F2838x Ethernet fifo and place them
 * into a pbuf queue.  If the transmitter is idle and there is at least one packet
 * on the transmit queue, it will place it in the transmit fifo and start the
 * transmitter.
 *
 */

Ethernet_Pkt_Desc*
f2838xif_interrupt(struct netif *netif, Ethernet_Pkt_Desc *pPacket)
{
    Ethernet_Pkt_Desc *sPacket = NULL;
    /**
     * Based on the flags we get from pPacket, we should decide whether
     * to trasnmit or receive. Currently, it works for only incoming
     * ICMP ping requests.
     */

    /* ENTER CRITICAL SECTION
     * This is to protect the forming of packetc descriptor chain using pbufs
     * passed to the function.
     */
    Interrupt_disable(INT_EMAC_TX0);
    Interrupt_disable(INT_EMAC_RX0);

    if(pPacket->flags & ETHERNET_INTERRUPT_FLAG_RECEIVE)
        sPacket = f2838xif_receive(netif, pPacket);

    if(pPacket->flags & ETHERNET_INTERRUPT_FLAG_TRANSMIT)
        f2838xif_process_transmit(netif, pPacket);

    /* EXIT CRITICAL SECTION */

    Interrupt_enable(INT_EMAC_TX0);
    Interrupt_enable(INT_EMAC_RX0);

    return (sPacket);
}

//###########################################################################
//
// FILE:   startup_ccs.c
//
// TITLE:  startup file for f2838x device.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright: $
//###########################################################################

//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
void ResetISR(void);
static void NmiSR(void);
static void FaultISR(void);
static void IntDefaultHandler(void);

//*****************************************************************************
//
// External declaration for the reset handler that is to be called when the
// processor is started
//
//*****************************************************************************
extern void _c_int00(void);

//*****************************************************************************
//
// Linker variable that marks the top of the stack.
//
//*****************************************************************************
extern unsigned long __STACK_END;

//*****************************************************************************
//
// External declarations for the interrupt handlers used by the application.
//
//*****************************************************************************
extern void lwIPEthernetIntHandler(void);
extern void SysTickIntHandler(void);

//*****************************************************************************
//
// The vector table.  Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000 or at the start of
// the program if located at a start address other than 0.
//
//*****************************************************************************
#pragma DATA_ALIGN(vectorTableFlash, 1024)
#pragma DATA_SECTION(vectorTableFlash, ".vftable")

void (* const vectorTableFlash[])(void) =
{
    (void (*)(void))((unsigned long)&__STACK_END),
                                            // The initial stack pointer
    ResetISR,                               // The reset handler
    NmiSR,                                  // The NMI handler
    FaultISR,                               // The hard fault handler
    IntDefaultHandler,                      // The MPU fault handler
    IntDefaultHandler,                      // The bus fault handler
    IntDefaultHandler,                      // The usage fault handler
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // SVCall handler
    IntDefaultHandler,                      // Debug monitor handler
    0,                                      // Reserved
    IntDefaultHandler,                      // The PendSV handler
    SysTickIntHandler,                      // The SysTick handler
    IntDefaultHandler,                      // GPIO Port A
    IntDefaultHandler,                      // GPIO Port B
    IntDefaultHandler,                      // GPIO Port C
    IntDefaultHandler,                      // GPIO Port D
    IntDefaultHandler,                      // GPIO Port E
    IntDefaultHandler,                      // UART0 Rx and Tx
    IntDefaultHandler,                      // UART1 Rx and Tx
    IntDefaultHandler,                      // SSI0 Rx and Tx
    IntDefaultHandler,                      // I2C0 Master and Slave
    IntDefaultHandler,                      // PWM Fault
    IntDefaultHandler,                      // PWM Generator 0
    IntDefaultHandler,                      // PWM Generator 1
    IntDefaultHandler,                      // PWM Generator 2
    IntDefaultHandler,                      // Quadrature Encoder 0
    IntDefaultHandler,                      // ADC Sequence 0
    IntDefaultHandler,                      // ADC Sequence 1
    IntDefaultHandler,                      // ADC Sequence 2
    IntDefaultHandler,                      // ADC Sequence 3
    IntDefaultHandler,                      // Watchdog timer
    IntDefaultHandler,                      // Timer 0 subtimer A
    IntDefaultHandler,                      // Timer 0 subtimer B
    IntDefaultHandler,                      // Timer 1 subtimer A
    IntDefaultHandler,                      // Timer 1 subtimer B
    IntDefaultHandler,                      // Timer 2 subtimer A
    IntDefaultHandler,                      // Timer 2 subtimer B
    IntDefaultHandler,                      // Analog Comparator 0
    IntDefaultHandler,                      // Analog Comparator 1
    IntDefaultHandler,                      // Analog Comparator 2
    IntDefaultHandler,                      // System Control (PLL, OSC, BO)
    IntDefaultHandler,                      // FLASH Control
    IntDefaultHandler,                      // GPIO Port F
    IntDefaultHandler,                      // GPIO Port G
    IntDefaultHandler,                      // GPIO Port H
    IntDefaultHandler,                      // UART2 Rx and Tx
    IntDefaultHandler,                      // SSI1 Rx and Tx
    IntDefaultHandler,                      // Timer 3 subtimer A
    IntDefaultHandler,                      // Timer 3 subtimer B
    IntDefaultHandler,                      // I2C1 Master and Slave
    IntDefaultHandler,                      // Quadrature Encoder 1
    IntDefaultHandler,                      // CAN0
    IntDefaultHandler,                      // CAN1
    IntDefaultHandler,                      // CAN2
    lwIPEthernetIntHandler,                 // Ethernet
    IntDefaultHandler,                      // Hibernate
    IntDefaultHandler,                      // USB0
    IntDefaultHandler,                      // PWM Generator 3
    IntDefaultHandler,                      // uDMA Software Transfer
    IntDefaultHandler,                      // uDMA Error
    IntDefaultHandler,                      // ADC1 Sequence 0
    IntDefaultHandler,                      // ADC1 Sequence 1
    IntDefaultHandler,                      // ADC1 Sequence 2
    IntDefaultHandler,                      // ADC1 Sequence 3
    IntDefaultHandler,                      // I2S0
    IntDefaultHandler,                      // External Bus Interface 0
    IntDefaultHandler                       // GPIO Port J
};

//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event.  Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.  Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
#pragma CODE_SECTION(ResetISR, ".resetisr")
void
ResetISR(void)
{
    // Jump to the CCS C Initialization Routine.
    __asm("    .global _c_int00\n"
          "    b.w     _c_int00");
}


//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI.  This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
static void
NmiSR(void)
{
    //
    // Enter an infinite loop.
    //
    while(1)
    {
    }
}

//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt.  This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
FaultISR(void)
{
    //
    // Enter an infinite loop.
    //
    while(1);
}

//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt.  This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
    //
    // Go into an infinite loop.
    //
    while(1)
    {
    }
}

//###########################################################################
//
// FILE:   enet_lwip.c
//
// TITLE:  lwIP based Ethernet Example.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright: $
//###########################################################################

#include <string.h>

#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_emac.h"

#include "driverlib_cm/ethernet.h"
#include "driverlib_cm/gpio.h"
#include "driverlib_cm/interrupt.h"

#include "driverlib_cm/sysctl.h"
#include "driverlib_cm/systick.h"
#include "driverlib_cm/flash.h"

#include "utils/lwiplib.h"
#include "board_drivers/pinout.h"

#include "lwip/apps/httpd.h"
//*****************************************************************************
//
//! \addtogroup master_example_list
//! <h1>Ethernet with lwIP (enet_lwip)</h1>
//!
//! This example application demonstrates the operation of the F2838x
//! microcontroller Ethernet controller using the lwIP TCP/IP Stack. Once
//! programmed, the device sits endlessly waiting for ICMP ping requests. It
//! has a static IP address. To ping the device, the sender has to be in the
//! same network. The stack also supports ARP.
//!
//! For additional details on lwIP, refer to the lwIP web page at:
//! http://savannah.nongnu.org/projects/lwip/
//
//*****************************************************************************

// These are defined by the linker (see device linker command file)
//extern unsigned long RamfuncsLoadStart;
//extern unsigned long RamfuncsLoadSize;
//extern unsigned long RamfuncsRunStart;

//*****************************************************************************
//
// Driver specific initialization code and macro.
//
//*****************************************************************************
#ifdef _FLASH

extern uint16_t RamfuncsLoadStart;
extern uint16_t RamfuncsLoadEnd;
extern uint16_t RamfuncsLoadSize;
extern uint16_t RamfuncsRunStart;
extern uint16_t RamfuncsRunEnd;
extern uint16_t RamfuncsRunSize;

#define DEVICE_FLASH_WAITSTATES 2

#endif

#define ETHERNET_NO_OF_RX_PACKETS   8U
#define ETHERNET_MAX_PACKET_LENGTH 500
#define NUM_PACKET_DESC_RX_APPLICATION 8

Ethernet_Handle emac_handle;
Ethernet_InitConfig *pInitCfg;
uint32_t Ethernet_numRxCallbackCustom = 0;
uint32_t releaseTxCount = 0;

uint32_t systickPeriodValue = 15000000;
Ethernet_Pkt_Desc  pktDescriptorRXCustom[NUM_PACKET_DESC_RX_APPLICATION];
extern uint32_t Ethernet_numGetPacketBufferCallback;
extern Ethernet_Device Ethernet_device_struct;
uint8_t Ethernet_rxBuffer[ETHERNET_NO_OF_RX_PACKETS *
                          ETHERNET_MAX_PACKET_LENGTH];

extern Ethernet_Pkt_Desc*
lwIPEthernetIntHandler(Ethernet_Pkt_Desc *pPacket);
void CM_init(void)
{
    //
    // Disable the watchdog
    //
    SysCtl_disableWatchdog();

#ifdef _FLASH
    //
    // Copy time critical code and flash setup code to RAM. This includes the
    // following functions: InitFlash();
    //
    // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
    // are created by the linker. Refer to the device .cmd file.
    //
    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

    //
    // Call Flash Initialization to setup flash waitstates. This function must
    // reside in RAM.
    //
    Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
#endif

    //
    // Turn on all peripherals
    //
    //CM_enableAllPeripherals();

    //
    // Sets the NVIC vector table offset address.
    //
#ifdef _FLASH
    Interrupt_setVectorTableOffset((uint32_t)vectorTableFlash);
#else
    Interrupt_setVectorTableOffset((uint32_t)vectorTableRAM);
#endif

}
//*****************************************************************************
//
// HTTP Webserver related callbacks and definitions.
//
//*****************************************************************************
//
// Currently, this implemented as a pointer to function which is called when
// corresponding query is received by the HTTP webserver daemon. When more
// features are needed to be added, it should be implemented as a separate
// interface.
//
void httpLEDToggle(void);
void(*ledtoggleFuncPtr)(void) = &httpLEDToggle;

//*****************************************************************************
//
// The interrupt handler for the SysTick interrupt.
//
//*****************************************************************************
void
SysTickIntHandler(void)
{
    //Interrupt_disable(INT_EMAC_TX0);
    //Interrupt_disable(INT_EMAC_RX0);
    //
    // Call the lwIP timer handler.
    //
    lwIPTimer(systickPeriodValue);
    //Interrupt_enable(INT_EMAC_TX0);
    //Interrupt_enable(INT_EMAC_RX0);
}

//*****************************************************************************
//
//  This function is a callback function called by the example to
//  get a Packet Buffer. Has to return a ETHERNET_Pkt_Desc Structure.
//  Rewrite this API for custom use case.
//
//*****************************************************************************
Ethernet_Pkt_Desc* Ethernet_getPacketBufferCustom(void)
{
    //
    // Get the next packet descriptor from the descriptor pool
    //
    uint32_t shortIndex = (Ethernet_numGetPacketBufferCallback + 3)
                % NUM_PACKET_DESC_RX_APPLICATION;

    //
    // Increment the book-keeping pointer which acts as a head pointer
    // to the circular array of packet descriptor pool.
    //
    Ethernet_numGetPacketBufferCallback++;

    //
    // Update buffer length information to the newly procured packet
    // descriptor.
    //
    pktDescriptorRXCustom[shortIndex].bufferLength =
                                  ETHERNET_MAX_PACKET_LENGTH;

    //
    // Update the receive buffer address in the packer descriptor.
    //
    pktDescriptorRXCustom[shortIndex].dataBuffer =
                                      &Ethernet_device_struct.rxBuffer [ \
               (ETHERNET_MAX_PACKET_LENGTH*Ethernet_device_struct.rxBuffIndex)];

    //
    // Update the receive buffer pool index.
    //
    Ethernet_device_struct.rxBuffIndex += 1U;
    Ethernet_device_struct.rxBuffIndex  = \
    (Ethernet_device_struct.rxBuffIndex%ETHERNET_NO_OF_RX_PACKETS);

    //
    // Receive buffer is usable from Address 0
    //
    pktDescriptorRXCustom[shortIndex].dataOffset = 0U;

    //
    // Return this new descriptor to the driver.
    //
    return (&(pktDescriptorRXCustom[shortIndex]));
}

//*****************************************************************************
//
//  This is a hook function and called by the driver when it receives a
//  packet. Application is expected to replenish the buffer after consuming it.
//  Has to return a ETHERNET_Pkt_Desc Structure.
//  Rewrite this API for custom use case.
//
//*****************************************************************************
Ethernet_Pkt_Desc* Ethernet_receivePacketCallbackCustom(
        Ethernet_Handle handleApplication,
        Ethernet_Pkt_Desc *pPacket)
{
    //
    // Book-keeping to maintain number of callbacks received.
    //
#ifdef ETHERNET_DEBUG
    Ethernet_numRxCallbackCustom++;
#endif

    //
    // This is a placeholder for Application specific handling
    // We are replenishing the buffer received with another buffer
    //
    return lwIPEthernetIntHandler(pPacket);
}

void Ethernet_releaseTxPacketBufferCustom(
        Ethernet_Handle handleApplication,
        Ethernet_Pkt_Desc *pPacket)
{
    //
    // Once the packet is sent, reuse the packet memory to avoid
    // memory leaks. Call this interrupt handler function which will take care
    // of freeing the memory used by the packet descriptor.
    //
    lwIPEthernetIntHandler(pPacket);

    //
    // Increment the book-keeping counter.
    //
#ifdef ETHERNET_DEBUG
    releaseTxCount++;
#endif
}

void
Ethernet_init(const unsigned char *mac)
{
    Ethernet_InitInterfaceConfig initInterfaceConfig;
    uint32_t macLower;
    uint32_t macHigher;
    uint8_t *temp;

    initInterfaceConfig.ssbase = EMAC_SS_BASE;
    initInterfaceConfig.enet_base = EMAC_BASE;
    initInterfaceConfig.phyMode = ETHERNET_SS_PHY_INTF_SEL_MII;

    //
    // Assign SoC specific functions for Enabling,Disabling interrupts
    // and for enabling the Peripheral at system level
    //
    initInterfaceConfig.ptrPlatformInterruptDisable =
                                                    &Platform_disableInterrupt;
    initInterfaceConfig.ptrPlatformInterruptEnable =
                                                     &Platform_enableInterrupt;
    initInterfaceConfig.ptrPlatformPeripheralEnable =
                                                    &Platform_enablePeripheral;
    initInterfaceConfig.ptrPlatformPeripheralReset =
                                                     &Platform_resetPeripheral;

    //
    // Assign the peripheral number at the SoC
    //
    initInterfaceConfig.peripheralNum = SYSCTL_PERIPH_CLK_ENET;

    //
    // Assign the default SoC specific interrupt numbers of Ethernet interrupts
    //
    initInterfaceConfig.interruptNum[0] = INT_EMAC;
    initInterfaceConfig.interruptNum[1] = INT_EMAC_TX0;
    initInterfaceConfig.interruptNum[2] = INT_EMAC_TX1;
    initInterfaceConfig.interruptNum[3] = INT_EMAC_RX0;
    initInterfaceConfig.interruptNum[4] = INT_EMAC_RX1;

    pInitCfg = Ethernet_initInterface(initInterfaceConfig);

    Ethernet_getInitConfig(pInitCfg);
    pInitCfg->dmaMode.InterruptMode = ETHERNET_DMA_MODE_INTM_MODE2;

    //
    // Assign the callbacks for Getting packet buffer when needed
    // Releasing the TxPacketBuffer on Transmit interrupt callbacks
    // Receive packet callback on Receive packet completion interrupt
    //
    pInitCfg->pfcbRxPacket = &Ethernet_receivePacketCallbackCustom;
    pInitCfg->pfcbGetPacket = &Ethernet_getPacketBufferCustom;
    pInitCfg->pfcbFreePacket = &Ethernet_releaseTxPacketBufferCustom;

    //
    //Assign the Buffer to be used by the Low level driver for receiving
    //Packets. This should be accessible by the Ethernet DMA
    //
    pInitCfg->rxBuffer = Ethernet_rxBuffer;

    //
    // The Application handle is not used by this application
    // Hence using a dummy value of 1
    //
    Ethernet_getHandle((Ethernet_Handle)1, pInitCfg , &emac_handle);

    //
    //Do global Interrupt Enable
    //
    (void)Interrupt_enableInProcessor();

    //
    //Assign default ISRs
    //
    Interrupt_registerHandler(INT_EMAC_TX0, Ethernet_transmitISR);
    Interrupt_registerHandler(INT_EMAC_RX0, Ethernet_receiveISR);

    //
    //Enable the default interrupt handlers
    //
    Interrupt_enable(INT_EMAC_TX0);
    Interrupt_enable(INT_EMAC_RX0);

    //
    // Convert the mac address string into the 32/16 split variables format
    // that is required by the driver to program into hardware registers.
    // Note: This step is done after the Ethernet_getHandle function because
    //       a dummy MAC address is programmed in that function.
    //
    temp = (uint8_t *)&macLower;
    temp[0] = mac[0];
    temp[1] = mac[1];
    temp[2] = mac[2];
    temp[3] = mac[3];

    temp = (uint8_t *)&macHigher;
    temp[0] = mac[4];
    temp[1] = mac[5];

    //
    // Program the unicast mac address.
    //
    Ethernet_setMACAddr(EMAC_BASE,
                        0,
                        macHigher,
                        macLower,
                        ETHERNET_CHANNEL_0);
}


//*****************************************************************************
//
// This example demonstrates the use of the Ethernet Controller.
//
//*****************************************************************************
int
main(void)
{
    unsigned long ulUser0, ulUser1;
    unsigned char pucMACArray[8];

    //
    // User specific IP Address Configuration.
    // Current implementation works with Static IP address only.
    //
    unsigned long IPAddr = 0xC0A80004;
    unsigned long NetMask = 0xFFFFFF00;
    unsigned long GWAddr = 0x00000000;
    CM_init();
    SYSTICK_setPeriod(systickPeriodValue);
    SYSTICK_enableCounter();
    SYSTICK_registerInterruptHandler(SysTickIntHandler);
    SYSTICK_enableInterrupt();

    //
    // Enable processor interrupts.
    //
    Interrupt_enableInProcessor();
        
    // Set user/company specific MAC octets
    // (for this code we are using A8-63-F2-00-00-80)
    // 0x00 MACOCT3 MACOCT2 MACOCT1
    ulUser0 = 0x00F263A8;

    // 0x00 MACOCT6 MACOCT5 MACOCT4
    ulUser1 = 0x00800000;

    //
    // Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
    // address needed to program the hardware registers, then program the MAC
    // address into the Ethernet Controller registers.
    //
    pucMACArray[0] = ((ulUser0 >>  0) & 0xff);
    pucMACArray[1] = ((ulUser0 >>  8) & 0xff);
    pucMACArray[2] = ((ulUser0 >> 16) & 0xff);
    pucMACArray[3] = ((ulUser1 >>  0) & 0xff);
    pucMACArray[4] = ((ulUser1 >>  8) & 0xff);
    pucMACArray[5] = ((ulUser1 >> 16) & 0xff);

    //
    // Initialize ethernet module.
    //
    Ethernet_init(pucMACArray);

    //
    // Initialze the lwIP library, using DHCP.
    //
    lwIPInit(0, pucMACArray, IPAddr, NetMask, GWAddr, IPADDR_USE_STATIC);

    //
    // Initialize the HTTP webserver daemon.
    //
    httpd_init();

    //
    // Loop forever. All the work is done in interrupt handlers.
    //
    while(1);
}

//*****************************************************************************
//
// Called by lwIP Library. Toggles the led when a command is received by the
// HTTP webserver.
//
//*****************************************************************************
void httpLEDToggle(void)
{
    //
    // Toggle the LED D1 on the control card.
    //
    GPIO_togglePin(DEVICE_GPIO_PIN_LED1);
}


//*****************************************************************************
//
// Called by lwIP Library. Could be used for periodic custom tasks.
//
//*****************************************************************************
void lwIPHostTimerHandler(void)
{

}