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Original question:

TMS320F28379D: DMA behavior

TMS320F28379D: DMA access (2)

CHRISTIAN VALPARD
Intellectual 340 points
Part Number: TMS320F28379D


Hi,

Sorry I'm back.

I have not really understant the sense of "pending" in the answer.

On  SPRUHM8I §5.6 "The priority scheme for GSx RAM accesses is round-robin."

§5.7.1 "after each channel has transferred a burst of words, the next channel is serviced." (CVA Note: CAUTION "after")

§3.11.1.6  Access Arbitration

I Don't really understand how it is possible to have CPU acces during a burst on a GSx RAM.

Best regards

Christian VALPARD

 

  • 0
    TI__Guru** 115971 points

    Hi Christian,

    As mentioned in other post, the term "Burst" does not mean back-to-back access. As mentioned earlier, DMA does read/write from same interface and DMA transfers have write followed by read or read followed by write. Let's say DMA channel is configured to do a BURST transfer from peripheral X to GSx RAM Y which means DMA will be reading data from peripheral X and writing it to GSx RAM Y. In this case DMA will Ist read data from X and then write to Y and then again read from X and then write to Y and so on. This basically means when DMA is doing read from X, there is no access on GSxRAM Y and that time if CPU tries to access GSxRAM Y (or if there was a pending access from CPU) then it will be granted the access. Right?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 340 points

    Hi Vivek,

    First thank you for your long answer and for the time spent for me.

    In spruhm8i

    §5.6 it's writen "A DMA transfer consists of four phases: send source address, read source data, send destination
    address, and write destination data (see Section 5.5). Suppose CPU accesses a peripheral / memory
    causing conflict in middle of a DMA transfer, CPU is stalled till the current DMA access is complete and
    not until the completion of whole DMA transfer."

    It's totally compliant with your explanation and I understand.

    I have found (§25.5.5.9) that on SDRAM "On this device, burst accesses are not supported, hence EMIF will issue READ
    command for each data access."  --> OK it's clear.

    But on GSxRAM if
    1) I set BURSTSIZE to 31 (cf. §5.9.3.3)
    2) Round Robin mode
    3) I start the DMA
    4) and immediatly after I whant to read with the CPU.

    What's going on ?
    §5.7.1 seems to me contradictory with the §5.6 because round robin mechanism seems to be activated after the completion of the burst.
    "After completing the CH1 burst, CH2 will be serviced since it is next in the round-robin scheme after
    CH1."

    I understand (§5.7.2) that with high priority mode bust can be interrupted "When the current CH4 word
    transfer is completed, regardless of whether the DMA has completed the entire CH4 burst, CH4 execution
    will be suspended and CH1 will be serviced. After the CH1 burst completes, CH4 will resume execution."

    From my point of view §5.6 is only true with High Priority mode.

    I hope I have been clear enough, and that you can tell me where I am wrong.

    Best regards

    Christian VALPARD