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Original question:

TMS320F28379D: ADCSOC for 2 cores using one PWM SOC

TMS320F28379D: Control ADC from CPU1 and CPU2

Patricio Peralta
Prodigy 120 points
Part Number: TMS320F28379D

Hello,

I am actually trying to control an electric drive with one of your Dual-CPU Delfino Launchpads.To do so, I am exploiting the Matlab Code Composer, so I am doing the programming in Simulink.

My general actual approach is to implement speed control on CPU1, and to implement current control CPU2. This will of course communicate via the IPC interface.

For the speed control, I have a 5 kHz ePWM interrupt, which generates an SOCA and SOCB, which reads the values of 6 hall sensors onto the ADCs.

Given that the ADC-A module is used multiple times, the SOC sequences is correspondly increased. On the other hand, ADC-B and ADC-C are tapped only once, so both are read at SOC0.

This is done by CPU1, and it works perfectly. It can be seen below.

As mentioned, I intend to control the current on CPU2. I use interrupt ePWM7 to launch the routine at 45 kHz. Inside the routine, the PWM 1- 2-3 modules from below, also switching at 45 kHz, generate their respective SOCA and SOCB to read the currents on ADC modules B and C.

I am now trying to test the current control and the sampling of the hall sensors at the same time.

The hall sensors from the the first picture can always be read with success. The problem arises when testing the current control.

The PWM modules for the current generate the SOCA and SOCB triggers that should be controlling the ADCs from above. If they are sampled with the same SOC than the hall sensors from CPU1, I end up reading their value, and not the value of the current. That I understand. Nevertheless, if I set them to sample with the subsequent SOC value, they do not sample at all... Thus the current control does not work.

Funnily enough, if I comment the ADC-B and ADC-C of the hall sensors (that is from CPU1), the currents are correctly sampled in CPU2. It is the same thing when I try running both routines on the same CPU : it actually works.

Does anyone have ideas to how I can correctly configure the ADCs so that the CPU1 and CPU2 can correctly share them ?

Thanks in advance,

Patricio

  • 0
    Prodigy 120 points

    Btw, I tried setting the SOCs of the first image (hall sensors, CPU1) starting from 0 - 5, and then setting those of the CPU2 to 6 and 7, and it still does not work.

    Yet, once again, when commenting those from ADC B and C from CPU1, the current control from CPU2 works perfectly.

    In some way, the exploitation of ADC B and C by CPU1 is 'blocking' its communication to CPU2, I believe....

    Thanks,

    Patricio

  • 0 in reply to Patricio Peralta
    TI__Guru 72765 points

    Patricio,

    From your description I suspect that there is an CPU1/CPU2 ownership issue in play.  For what you've described I'd like to confirm if you have this set as follows:

    ADC A/B/C  -all owned and configured by CPU1(even for the current control sampling)

    Speed Control PWMs - CPU1

    Current Control PWM(s) -CPU2

    Even though the ADC is "owned" by CPU1 you can still configure the SOCs for the current control to be triggered from the PWM that is owned by CPU2.

    The ADCINTs go to both CPUs in parallel, so you just need to set one set of INTs for Speed control signals and CPU1 will enable that, and another INT for CPU2, which it will enable.

    Finally, no matter the CPU ownership both CPUs can read the ADC Result registers.  I am not 100% if the ADC Result regs are dual port, meaning if they can support a simultaneous read from both CPUs(if the timing of your conversions is just right), but at a worst case the read wouldn't be lost it would just pend until the other CPU read is complete.

    The individual ADCs can only have one CPU controlling them, but for the intent of the system you could think of it as one CPU can configure an ADC.  For ADC setups these are usual set during an init and largely left alone.

    Let me know if this resolves things.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 120 points

    Hello Matthew,

    Thank you for your swift and precise response.

    Thanks to your indications, the code now works. It was key to know that the ADCs can only have one CPU controlling them.

    I was actually trying to configure the ADCs on different CPUs; that is, I was configuring the ADCs A/B/C of speed control on CPU1 and the ADCs B/C for current control on CPU2.

    Now, I just added the current control ADCs B/C to CPU1. They are succesfully configured, and I can read them with no problems from CPU2 (have not tried yet to read them simultaneously, i.e. also in CPU1).

    Best,

    Patricio

  • 0 in reply to Patricio Peralta
    TI__Guru 72765 points

    Glad this was the issue and helped you get things working.  I did confirm that the ADC Result Registers are dual port, meaning you can access with CPU1 and CPU2 simultaneously without any performance hit to either CPU.  

    Best,
    Matthew