Other Parts Discussed in Thread: C2000WARE
Hello, I'm trying the IDLE low power mode example using XINT1 (#define WD_WAKE commented). I have a current measurement at JP1 on the launchxl-F28379D board and I'm watching GPIO1 to see when the DSC wakes. I would like to understand why the 3.3V rail current at JP1 is much high than expected before waking. Before wake the current is 142mA and after wake it is 159mA.
From the datasheet I expected Idd to change from 80mA to 245mA approximately. Assuming a 85% efficiency in converting 3.3V to 1.2V I expected to see approximately a 71mA change at the 3.3V rail based on the following; (245mA -80mA) * 1.2V/3.3V /0.85 = 71mA .
By reducing the PLL multiplier the scope shows significant current savings. I was hoping to see the same from IDLE since it gates the CPU clock. Any help with this C200Ware LPM example would be much appreciated, thanks.