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Original question:

TMS320F28388D: Power up RAM Test for on-chip SRAM

TMS320F28388D: Software access to SPI FIFO Buffer Access

Amulrass Vazhumuni
Intellectual 435 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hello ,

I am working on SPI module on TMS320F28388D device. I intend to use the SPI module in FIFO mode, but in the TRM, it is not clearly mentioned how to access SPI TX and RX FIFO buffers (FIFO_0 to FIFO_15) by the software. Is there any way to directly write into FIFO Tx Buffer?

In Non-FIFO mode, what will be the content of this register SPIFFTX.TXFFST bits? Is it always zero?

Best Regards

Amulrass V  

  • 0
    TI__Mastermind 32565 points

    Hi Amulrass,

    When FIFO is enabled, any write to TXBUF writes to the TX FIFO and any read from the RXBUF register reads from the RX FIFO. Please refer to the examples available in C2000ware to see how these are used.

    Regards,

    Veena

  • 0 in reply to Veena Kamath
    Intellectual 435 points

    Hello Veena,

    So, there is no way to for software to directly access the TX and RX FIFO buffers. Writing into TXBUF automatically push the data into FIFO Queue, and similarly reading from RXBUF automatically removes the oldest data from the FIFO.

    It is better to add this information in TRM to ease the software development. 

    What about my another Query: In Non-FIFO mode, what will be the content of this register SPIFFTX.TXFFST bits? Is it always zero?

    Best Regards

    Amulrass V

  • 0 in reply to Amulrass Vazhumuni
    TI__Mastermind 32565 points

    Hi Amulrass,

    You are right, There is no way to access the FIFO buffers directly. The accesses to the TXBUF and RXBUF will internally access the respective FIFOs.

    Amulrass Vazhumuni said:
    In Non-FIFO mode, what will be the content of this register SPIFFTX.TXFFST bits? Is it always zero?

    I believe it will remain zero. I am checking with the module expert on this. I believe it will be good add this information as well in the TRM.

    Regards,

    Veena

  • 0 in reply to Veena Kamath
    TI__Mastermind 28991 points

    In non-FIFO mode the FIFO would remain in reset (SPIFFTX.TXFIFO = 0) and the FIFO pointer would be set to zero. Also, note that in non-FIFO mode you shouldn't write more than one character to SPITXBUF, otherwise you will get an overrun condition.

  • 0 in reply to Gus Martinez
    Intellectual 435 points

    Hello,

    Thanks. I understood the behavior of the SPI FIFO buffer. I have another question on the SPICHAR?

     I need to do SPI transmission using two different data length in non-FIFO mode. Some of the SPI Tx messages, I have to send using 16-bit data length and some of the SPI messages as 8-bit data length. So, I intend to change SPICHAR at the runtime in non-FIFO mode.

    What is the effect of SPICHAR modification, on the ongoing SPI transmission? i.e. during the shifting out of data from SPIDAT, the software modifies SPICHAR and writes new data onto TXBUF.

    Best Regards

    Amulrass V

  • 0 in reply to Amulrass Vazhumuni
    TI__Mastermind 28991 points

    If you plan to have the CPU control the SPISTE pin directly (i.e. configure it as GPIO), then the easiest thing to do would be to use 8-bit characters all the time. During transmission, the CPU would set the GPIO pin (SPISTE) low, send 1 or 2 8-bit characters, and set the GPIO pin high. You can use the INT_FLAG bit to monitor the status of the transmission. 

    If you want to have the SPI control the SPISTE pin directly, you can switch SPICHAR configuration, but you need to ensure the character has been fully transmitted before doing so. Again, you can use the INT_FLAG bit for that.

  • 0 in reply to Gus Martinez
    Intellectual 435 points

    Hi,

    Thanks for the information.

    Best Regards

    Amulrass V