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Original question:

TMS320F28388D: T-FORMAT library source code

TMS320F28388D: tformat lib change pin

Lei Yang3
Prodigy 40 points
Part Number: TMS320F28388D


Hello,

I use the 28388D controlcard with the POSMGR to test the tamagawa tformat encoder.

By default, the PWM4B (GPIO7) is used to generate clock signal and TxEn (GPIO9) is to generate the transmit/receive signal.

However, in our future design, the PWM1-PWM6 are required to generate the PWM signal and cannot be used for the above funtion.

So, could I change the pin GPIO7 and GPIO9, and how could I implement this.

Many thanks for your help.

Best wishes

Lei

  • 0
    TI__Guru* 92750 points

    Hello,

    The pins can be changed.  There are some limitations based on which CLB tile you are using and which output from the tile. The C2000 Key Technology guide lists resources for learning about and modifying the CLB configuration (https://www.ti.com/lit/spracn0)  Refer to the CLB resource list on page 46.

    Also note that depending on the change you make, it may not be compatible with the boosterpack or IDDK pinout.  The schematics for the boosterpack can be downloaded with the design files on the product page (https://www.ti.com/tool/BOOSTXL-POSMGR)

    Here are a couple of posts with related information:

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/959356

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/933372

    Lori 

  • 0 in reply to Lori Heustess
    Prodigy 40 points

    Thanks for your reply.

    Now I made some progress in the pin change, but there is a problem.

    GPIO7 (clocking singal from) is generated in the CLB4_OUT2_0 and I want to change it.

    The CLB4_OUT5_1 can access to the output xbar so I think if I replicate the OUT5 from OUT2 and then I can get the clocking signal from any output xbar pin.

    The diagram is as follows.

    And I did the simulation, the signals from top to botom is the out2 to out 5.

    The I choose the GPIO14 which can access the CLB4_OUT5_1 via OUTPUTXBAR3.

    The resuls is different from the simulation. OUT2, OUT4 and OUT5 are shown.

    I am not sure why there is a 3us notch before the clocking signal in the green waveform (GPIO14).

    Many thanks

    Best wishes

    Lei

  • 0 in reply to Lei Yang3
    TI__Guru* 92750 points

    Lei Yang3 said:
    I am not sure why there is a 3us notch before the clocking signal in the green waveform (GPIO14).

    Lei,

    This could be caused by the GPIO setup of the pin.  This is not accounted for by the CLB simulation.  Is everything as you expect for the next transmission?

    -Lori

  • 0 in reply to Lori Heustess
    Prodigy 40 points

    Hi Lori,

    I have checked the GPIO configuration. 

    GPIO14 is set the same as GPIO7.

    The notch exists every time when the transmission begins.

    By the way, what is the CLB output 3.

    Best wishes

    Lei

  • 0 in reply to Lei Yang3
    TI__Guru* 92750 points

    Lei,

    Good to hear that your modifications match the original.  I don't think this notch will impact the communication.   The transmission of the request from the interface should be fine.  Are you seeing differently?

    Lei Yang3 said:
    By the way, what is the CLB output 3.

    This is the enable for the pwm pin - ref Figure 2-8. CLB Outputs – HLC Event0 and EPWM Output Enable

    Regards

    Lori