TMS320F28388D: T-FORMAT library source code

Lori Heustess said:

If you want to override a PWM pin to output SPICLK then yes, which PWM is connected to the tile output boundary signals depends on the tile.  PWM1 being tied to TILE1, PWM2 to TILE2 etc.  

Another option would be to move the SPICLK to CLB output 4 or 5.  Both of these have the ability to connect to the OUTPUT XBAR on all tiles which gives more flexibility in which GPIO is used.   In the example design output 5 is currently not used.   If you use a GPIO then change the code which sets the pin to a known state (currently uses the TZ functionality of the ePWM) by writing to the GPIO. 

If I move SPICLK to CLB4_OUT5_1, then I can connect it to OUTPUT XBAR and output to more GPIOs, this should work.

So just want to confirm that the reason why we use CLB output to override PWM4B rather than directly output from other general GPIO is just to use TZ function to set the this pin high during idle state, is this correct? If so, then this function can totally replaced by writing the GPIO registers, 

Thanks Lori.

Lori Heustess said:

Another option would be to move the SPICLK to CLB output 4 or 5.  Both of these have the ability to connect to the OUTPUT XBAR on all tiles which gives more flexibility in which GPIO is used.   In the example design output 5 is currently not used.   If you use a GPIO then change the code which sets the pin to a known state (currently uses the TZ functionality of the ePWM) by writing to the GPIO. 

Hi Lori,

As you suggest, I copy OUTLUT2 to OUTLUT5 and output the SPICLK to CLB4_OUT5.1 through XBAR_OUTPUT1 GPIO24, we also re-mapping the 485 enable to GPIO61, the SPIFIFO ISR can work and I can get the T-format encoders feedback data, but the position data seems not correct and the code report CRC error from time to time (PWM do not work yet). Here is the scope we got, channel 1 is SPICLK and channel 2 is RS485 enable, seems the TxEN (transmit enable) for the RS485 transceiver data line do not always held high during transmit data phase, this should not match the Signal Timing and State Transitions. Do you have any suggestion? Is this lead to CRC error and wrong data?

Thanks.

Samsai said:

As you suggest, I copy OUTLUT2 to OUTLUT5 and output the SPICLK to CLB4_OUT5.1 through XBAR_OUTPUT1 GPIO24, we also re-mapping the 485 enable to GPIO61,

Sam,

Just to make sure, this configuration is on the customer's board, correct? 

Samsai said:

the position data seems not correct and the code report CRC error from time to time

Is the data always incorrect?  You mention the CRC is sometimes incorrect which is odd - it sounds like it could be a noise issue if it is random? 

Samsai said:

PWM do not work yet

Not sure what this means? Can you clarify?

Samsai said:

TxEN (transmit enable) for the RS485 transceiver data line do not always held high during transmit data phase

It should be high in order to turn the transceiver on the customer's board to transmit.  If it is turned to receive too soon then all of the information won't make it to the encoder. 

-Lori

Lori Heustess said:

Just to make sure, this configuration is on the customer's board, correct? 

Yes, on customer board.

Lori Heustess said:

Samsai

the position data seems not correct and the code report CRC error from time to time

Is the data always incorrect?  You mention the CRC is sometimes incorrect which is odd - it sounds like it could be a noise issue if it is random?

Sometimes the CRC is correct and sometimes it is not, the position data will jitter suddenly even when the motor blocked, and if we just ignore the CRC failed frame, the position data jitter will disappear. We test on DC 5V supplied control board, there is no power stage and so there should be no noise.

Lori Heustess said:

Samsai

PWM do not work yet

Not sure what this means? Can you clarify?

This means we do not have power stage and do not output PWM, so there is no switching noise.

Lori Heustess said:

Samsai

TxEN (transmit enable) for the RS485 transceiver data line do not always held high during transmit data phase

It should be high in order to turn the transceiver on the customer's board to transmit.  If it is turned to receive too soon then all of the information won't make it to the encoder.

This is also my question, most of the CLB include TxEN part is exactly the same with the example code, but I am not sure if this Signal Timing in the oscilloscope is correct or not? We use 17bit and 23bit TAMAGAWA encoders, but the results are the same. We set the SPICLK output GPIO24 as you suggest, is this make sense? 

void PM_tformat_setFreq(uint32_t freq_us)
{
    EALLOW;
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_COUNTER_0_MATCH1, (freq_us - 1));
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_COUNTER_0_MATCH2,
            ((2 * freq_us) - 1));
    CLB_setGPREG(CLB4_BASE, 0x80);
    //-------------------------
    //Set SPICLK GPIO to 1
    GPIO_writePin(24, 1);
    //-------------------------
    EDIS;
}

void tformat_resetCLB(void)
{

    CLB_setGPREG(CLB4_BASE, 0);
    //-------------------------
    //Set SPICLK GPIO to 1
    GPIO_writePin(24, 1);
    //-------------------------

    //
    // Turn OFF the CLB functionality
    //
    EALLOW;
    HWREG(CLB4_BASE + CLB_LOGICCTL + CLB_O_LOAD_EN) = 0;
    EDIS;

    //
    // Clear Counters - this will clear counter REGs. Add_shift_on_even_en
    // should be Zero for this to take effect.
    //
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_COUNTER_0_LOAD, 0x0);
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_COUNTER_1_LOAD, 0x0);
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_COUNTER_2_LOAD, 0x0);

    //
    // Clear and reload the HLC registers
    //
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_HLC_R0, 0x9);
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_HLC_R1, 0x0);
    CLB_writeInterface(CLB4_BASE, CLB_ADDR_COUNTER_1_MATCH1, 0x2);

    CLB_setOutputMask(CLB4_BASE, 0, false);

}

Samsai said:

but I am not sure if this Signal Timing in the oscilloscope is correct or not? We use 17bit and 23bit TAMAGAWA encoders, but the results are the same.

Sam, 

The waveform shows TxEn with respect to the SPICLK.  Can you check what it looks like with respect to DATA_OUT?  TxEn changes the direction of send/receive for DATA_IN/DATA_OUT.

Samsai,

Was this resolved?

Regards

Lori