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Original question:

LAUNCHXL-F28069M: Cannot boot from Flash on power up

LAUNCHXL-F28379D: SCI-A reset when can not boot from Flash on power up

Sergio Reche Velasco
Intellectual 295 points

Part Number: LAUNCHXL-F28379D

Hello!
Looking for the solution of not being able to communicate via serial port SCI-A when I boot from Flash on power up, I found that another user solved it by activating the interrupt error SCI-A RX and restarting SCI-A. It appears to be a known issue in the LaunchPadXL.
But how exactly?

1.- How are the steps to activate this SCIA_RX_ISR interrupt?
2.- What instructions do I need to restart SCI-A? The same as to start it (typical scia_init function)?

The thread of another user: https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/664624
And the solution proposed by  :

[...]
Looks like the FTDI chip booting up causes errors on the SCI-A RX line (if you have your board configured to use SCI-A for USB-to-serial coms). All I had to do was enable the interrupt for errors on SCI-A RX, and reset SCI-A when they occurred.
[...]

Thanks!
Best regards.

  • 0
    TI__Mastermind 27190 points

    Hi SrgiO,

    SrgiO said:
    not being able to communicate via serial port SCI-A when I boot from Flash on power up

    Do you see anything in your serial port?

    SrgiO said:
    How are the steps to activate this SCIA_RX_ISR interrupt?

    You can enable interrupts when an error is detected through the RXERRINTENA bit of the SCICTL1 register. I would suggest doing this in your SCI initialization function. 

    Snippet from the Technical Reference Manual (TRM) below shows that writing a 1 to this bit will enable interrupts for any error detected.

    Within your interrupt service routine you can do something like this:

    if(SciaRegs.SCIRXST.bit.RXERROR){
    SciaRegs.SCICTL1.bit.SWRESET=0; 
    SciaRegs.SCICTL1.bit.SWRESET=1;
}

    The explanation of RXERROR bit is as follows:

    SrgiO said:
    What instructions do I need to restart SCI-A? The same as to start it (typical scia_init function)?

    Notice that in the segment of code I provided above the SWRESET bit of the SCICTL1 register was modified, this was to restart the SCI module in case there were any errors that were detected. Refer to Table 19-9. SCICTL1 Register Field Descriptions within the TRM (link provided above) for further details on the SWRESET bit such as which bits get modified.

    Best Regards,

    Marlyn