This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280025: can lower ISR can nest higher ISR?

Part Number: TMS320F280025
Other Parts Discussed in Thread: C2000WARE

Hi expert,

it seems that the demo code [interrupt_ex2_sw_prioritization] can achieve lower ISR can nest higher ISR.

which locates at:

C:\ti\c2000\C2000Ware_3_03_00_00\driverlib\f28002x\examples\interrupt

however, in the describtion, it highlights that only [higher user priority to be serviced].

and I did not see any re-prioritized PIE in the demo code?

how to really understand the nesting method, whether only with this, can achieve lower ISR nest higher ISR?

BR,

Emma

  • Hi Emma,

    Thanks for your question. As stated in the description, the priorities of the three CPU timers is switched using software. So instead of CPU0 timer being the highest priority, in the script, CPU2 timer is the highest priority:

    //! In this device, hardware priorities for CPU Timer 0, 1 and 2 are set
    //! as timer 0 being highest priority and timer 2 being lowest priority.
    //! This example configures CPU Timer0, 1, and 2 priority in software with
    //! timer 2 priority being highest and timer 0 being lowest in software and
    //! prints a trace for the order of execution.

    This is achieved in each cpuTimer#ISR function, see highlighted note below for where this occurs.

    //
    // cpuTimer0ISR - Counter for CpuTimer0
    //
    __interrupt void
    cpuTimer0ISR(void)
    {
        //
        // Save IER register on stack
        //
        volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);
    
        //*****HIGHLIGHTED SECTION*****
        // Set the global and group priority to allow CPU interrupts
        // with higher priority
        //
        IER |= M_INT1;
        IER &= MINT1;
        HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;
        //*****END HIGHLIGHTED SECTION*****
        ...
    

    This function above is the basis of reprioritizing the PIE. The PIE block itself is the same, but the software changes which interrupts get serviced by modifying the global and group priority (see highlighted section above). If this is not clear, please view the following wiki page on the subject:

    https://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

    Regards,

    Vince

  • Unfortunately, the wiki is removed since Jan, 15th. Where are the "migrated appropriate pages on TI.com" ?

  • Hi Stephan,

    I apologize, you are correct that the wiki has been removed, and this particular information has instead been moved to within the C2000Ware library at the following location (it is also mentioned in the example itself as a comment in the description section):

    //! Refer to below link on more details on Interrupt nesting in C28x devices:
    //! <C2000Ware>\docs\c28x_interrupt_nesting\html\index.html

    Please see the "Adding Simple Software Prioritization (Nesting)" section of the page.

    Regards,

    Vince

  • Hi Vince,

    ah, I see. Thanks for pointing to the docs.

    Regards,
    Stephan