TMS320F28375D: When does I2CCNT get written to internal data counter?

Jiri,

- set I2CMDR anew for TX, this time with STT=0 (since we already sent one) but SCD=1 (so I get a stop condition at the end)

The last step immediately generates a stop condition, which would hint that the internal data counter is still zero.

I played around some more and it seems I2CCNT gets written into internal data counter when generating start condition. (That's just a speculation, but feel free to confirm or correct me)

Unfortunately start condition resets my device's bus cycle so I can't really use repeated start condition.

To generate a repeated start condition, you shouldn't generate STOP condition after address bytes are transmitted. Your speculation is indeed correct. When you generate second START condition, it was waiting for sending / receiving I2CCNT number of bytes.

Here is the procedure to generate repeated START condition:

- Make sure STP bit isn't SET.

- set I2CMDR = IRS | MST | TRX | STT

- set I2CCNT 2

- write 2 bytes

- then wait for ARDY and clear it

- Set I2CCNT bit again to number of bytes transmitted / received

- Generate repeated START condition by setting STT bit

- You can now have STP condition set in I2CMDR to generate STOP condition

Regards,

Manoj