TMS320F28388D: Is it possible to reload PWM output twice during one PWM period.

Yes it is possible to load CMPA twice in each PWM cycle (ZERO to PRD to ZERO).

But you have to write the first value before ZERO event, then second value between ZERO and PRD events. 

Nima

Hello,

Thank you for reply.

In my understanding, it was implemented to “write the first value before ZERO event, then second value between ZERO and PRD events” by the following C code.
The following C code is running in the PWM interrupt routine generated on the timing of time-base counter equal to zero or period.
With this C source, the first value before ZERO should be 0.5*period, the second value between ZERO and PRD should be 0.1*period.
But, from the PWM waveform, it shows only 0.5*period was implemented.
{
status = EPwm1Regs.TBSTS.bit.CTRDIR;

if (1U==status)

{m_set = 0.1*period;}

else if (0U==status)

{mu = 0.5*period;}

else{}
}

Here is the related register configurations.

- High-resolution deadband, duty and phase control are enabled

- Up-down count mode
{EPwm1Regs.TBCTL.bit.CTRMODE = 2U;}

- Enable PWM interrupt event: time-base counter equal to zero or period (TBCTR= 0x00 or TBCTR = TBPRD).
{EPwm1Regs.ETSEL.bit.INTSEL = 3U;}

- Active Counter-Compare A (CMPA) Load From Shadow Select Mode Load: on either CTR = Zero or CTR = PRD
{EPwm1Regs.CMPCTL.bit.LOADAMODE =2U;}

I would appreciate any suggestions on this issue.

Best Regards,

Wenjing

Is your CMPA in shadow load mode?

Can you double check the question above in your code?

Hi, Nima

I am a colleague of Wenjing.

On her behalf, I reply.

EPwm1Regs.TBCTL.bit.PRDLD = 0;

0: The period register (TBPRD) is loaded from its shadow register
when the time-base counter, TBCTR, is equal to zero and/or a sync
event as determined by the TBCTL2[PRDLDSYNC] bit.
A write/read to the TBPRD register accesses the shadow register

EPwm1Regs.TBCTL2.bit.PRDLDSYNC = 0;

PRDLDSYNC
Shadow to Active Period Register Load on SYNC event
00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0
(same as legacy).
01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0
and when SYNC occurs.

Could you let us know what value we should on PRDLDSYNC  ?

Best regards,

Hidehiko

>Either 00 and 01 should work for PRDLDSYNC

Loaded condition

PRDLDSYNC=00  only when TBCTR = 0

PRDLDSYNC=01   both when TBCTR = 0 and when SYNC occurs.

PRDLDSYNC=10   bonly when a SYNC is received.

PRDLDSYNC=01 

we should write the first value before ZERO event,
then second value between ZERO and PRD events.

In that case, duty is updated twice in a period of a carrier period (between counter 0 -> top -> 0 ).

Best regards,

Hidehiko

Hello, Nima

Sorry for the late feedback.

CMPA  is in shadow load mode.

My original question is “can duty value of CMPA/B be changed twice in a PWM cycle.

Now, I have confirmed it works fine.

I realized:
if high resolution period feature is enabled by Epwm1Regs.HRPCTL.bit.HRPE = 1U;  
The duty value can only be loaded once on TBCTR=0.
if high resolution period is disabled by Epwm1Regs.HRPCTL.bit.HRPE = 0U;  
The duty value can be loaded twice.

Does it mean HR period feature must be disabled if using duty twice update in a PWM cycle.

Best Regards,

Wenjing 

Precisely. If you use HRPWM mode, you can only update your duty ONCE per PWM cycle. The second shadowing which you had during NON-HR mode, is now used by HR-Mode internally, so you can't use it for your application.

Please click the green verified answer button.

Nima

Hi Nima,

Thank you for your answer.
Does your “ use HRPWM mode” mean HR period control is enabled?
If yes, is following my understanding correct?

Configure the registers as:
Epwm1Regs.HRPCTL.bit.HRPE = 1U; /** HR period control is enabled**/
Epwm1Regs.HRCNFG.bit.HRLOAD = 2U; /** CMPAHR shadow value Load on either CTR = Zero or CTR = PRD **/
But the result is the CMPA shadow value is loaded into the active register only at CTR=ZERO.

Could you please take a look at the additional questions?

1. When enabling HR period control and Using TRREM,
HR Phase control works fine when TBPRHR = 0,
HR Phase control appears a jitter when TBPRHR != 0, and it seems the higher the TBPRHR value, the greater the jitter.
Could you let me know the reason or the cause?

2, If disable HR period control, will the HR duty control (CMPAHR) not work?

Best Regards,

Wenjing