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TMS320F280049C: a problem in 280049 CLA debug

Part Number: TMS320F280049C

now in my project i use CLA, but i have a prolem, i use PWM7 TBCTR=CMPB as CLA trigger, and i can go into the CLA code to run , but i find all PWMx.TBPRD=0xFFFF (initial value is not 0xFFFF)

so i try to find the reason through step debug, and i find when step over "EPwm7Regs.ETSEL.bit.INTEN = TRUE; " and the all PWMx.TBPRD=0xFFFF

this is my PWM7 trigger initial code:  what's the reason?? thank you!

/**************************************************************************************/
// EPWM Module 7 config: For ISR and ADC trigger
EPwm7Regs.TBPRD = PWM_INTPRD; //20160121 change to 45k Isr frequency!!
EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up/dn

EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm7Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm7Regs.TBPHS.bit.TBPHS = 2;
EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // disable sync out
//TBCLK=SYSCLKOUT/(HSPCLKDIV * CLKDIV)=SYSCLKOUT
EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1; //Timebase clock pre-scale
EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //High speed time pre-scale
EPwm7Regs.CMPB.bit.CMPB = INT_CMPB;

EPwm7Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPB;
EPwm7Regs.ETSEL.bit.INTEN = 0; // Disable INT
EPwm7Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm7Regs.ETCLR.all = 0x000F ; //clear all ETFLAG

  • Hi,

    Are you running the above code from CPU or CLA?
    Are you observing similar behavior when you run the code from CPU?
    There is no relation between Interrupt being enabled and TBPRD value changing to 0xFFFF.
    Instead of viewing in the debugger window, can you read the TBPRD value from the code and confirm what value it returns?

  • sorry, it's my problem; since in CLA my code has writted PWM.PRD register, and the write value  is wrong calculated to 0xFFFF;

    so when the "EPwm7Regs.ETSEL.bit.INTEN = TRUE" is run ,and cla code start to run and the PWM.PRD value is writted by 0xFFFF