TMS320F28377D: CLA1 couldn't read/write to assigned LS memory.

HI Lily,

Are you able to read/write to L1 RAM locations via CCS memory watch window ? Also in CCS register view please check the value of MSEL_LS1 bit to make sure it has correct value after executing the code to update this register.

Regards,
Vivek Singh

Hi Vivek,

Yes, I am able to read/write LS1 via CCS memory watch window.

In the Register view: MSEL_LS1 is 01, CLAPGM_LS1 is 0.

Thanks,

Lily.

Hi LiLy,

Did you verify MemCfgRegs.LSxMSEL.bit.MSEL_LS1 is set as you expect after initialization? I mean perhaps EALLOW is missing, which could break initialization.

Edward

Hi Edward,

The initialization is completed (EALLOW is set). I have verified MES_LS1 register after executing the code.

void CLA_configClaMemory(void)

{

extern uint32_t Cla1ProgRunStart, Cla1ProgLoadStart, Cla1ProgLoadSize;

extern uint32_t Cla1mathTablesRunStart, Cla1mathTablesLoadStart, Cla1mathTablesLoadSize;

EALLOW;

#ifdef _FLASH

// Copy over code from FLASH to RAM

memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart,

(uint32_t)&Cla1ProgLoadSize);

memcpy((uint32_t *)&Cla1mathTablesRunStart, (uint32_t *)&Cla1mathTablesLoadStart,

(uint32_t )&Cla1mathTablesLoadSize);

#endif //_FLASH

// Initialize and wait for CLA1ToCPUMsgRAM

MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;

while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};

// Initialize and wait for CPUToCLA1MsgRAM

MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;

while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};

// Select LS5RAM to be the programming space for the CLA

// First configure the CLA to be the master for LS5 and then

// set the space to be a program block

MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;

MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;//CLA Program memory

//Next configure LS0RAM as data spaces for the CLA

// First configure the CLA to be the master for LS0 and then

// set the spaces to be code blocks

// MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;

// MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;

//Next configure LS1RAM as data spaces for the CLA

// First configure the CLA to be the master for LS1 and then

// set the spaces to be data blocks

MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;

MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;//CLA Data memory

EDIS;

}

Thanks,

Lily.

Hi Lily,

Have you checked if this issue exist on another part as well ?

Vivek Singh 

HI Vivek,
Yes, I have checked the code on two boards. They are the same PCB and built the same time, have the same issue. FYI, the problem doesn't show on the previous TMX part, but it is a earlier version PCB as well.
Thanks,
Lily.

This is really strange. Can you try other LSx RAM e.g. LS0/LS2? Also have you checked if CPU is able to RD/WR to this RAM from code?

Vivek Singh

Hi Vivek,
I have tried LS3, it had the same issue.

CPU has no issue RD/WR to this RAM. The memories initialized by CPU are correct. The CPU routine can change the values as well during the execution.

Thanks,
Lily,

HI Vivek,

Some extra information: CLA1 doesn't have problem RD from "CpuToCla1MsgRAM" and WR to "Cla1ToCpuMsgRAM".

Thanks,

Lily.

Ok. That one does not have any configuration so a bit different. From which RAM, CLA is executing the code from?

Vivek Singh

Hi Vivek,
LS5.
Thanks,
Lily

Hi Vivek,

From LS5.
Thanks,

Lily.

LS5.
Thanks,
Lily

Hi Lily, 

This look very strange. Can you change the cmd file to use the RAM which is used for execution right now, for data read/write and see if that works? Basically want to know if issue is only with read/write for all LSx RAM and execution is fine.

Vivek Singh

Hi Vivek,

After I changed the CLA Data RAM to LS5 and Program to LS1 in cmd file, modified MSEL, the CLA didn't start properly and the NMAVFLG CLA1FECH flag was set.

Then I kept Data RAM in LS5, changed Program to LS4, it worked better. CLA started again and was able to read/write to LS5.

Thanks for your help,

Lily.

Hi Vivek,

Does my previous post provide enough information?

Please let me know if there are more tests you want me do.

Thanks,

Lily.

Ok, so issue is with LS1 and LS3 and LS4/LS5 works. What about LS0 and LS2? Are they ok ?
I know you mentioned that this work fine on TMX device. But have you run the exact same .out or it was run earlier. If that info is based on earlier run then can you try running exact same .out on TMX device and see if it works fine. Other thing to check is after CLA start executing the code, please check the MSEL settings in register for LSx RAMs.

Can you also take the picture of the device (top view) and send me. Want to check the lot number for these TMS part.

Regards,

Vivek Singh

Hi Vivek,

Yes. The issue is in LS0, LS1, LS2 and LS3.

TMX and TMS devices are running the exact same .out files (with our code, and with TI controlSUITE sample project). TMX works fine with both, and TMS has issue with both.

The TMS part picture is attached.

Thanks,

Lily

Discussing this offline.